From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Turquette Subject: Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control Date: Sat, 15 Jun 2013 21:22:56 -0700 Message-ID: <20130616042256.7541.7096@quantum> References: <20130607121505.21868.72360.stgit@dusk.lan> <20130607121901.21868.65416.stgit@dusk.lan> <51B21105.1080301@wwwdotorg.org> <51B6D239.5030905@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Paul Walmsley , Prashant Gaikwad Cc: Stephen Warren , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Peter De Schrijver , Aleksandr Frid , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-tegra@vger.kernel.org Quoting Paul Walmsley (2013-06-11 02:47:13) > On Tue, 11 Jun 2013, Prashant Gaikwad wrote: > > > Why not implement these APIs in DFLL clock driver itself and pass RST address > > register to driver? > > The DFLL DVCO reset registers are CAR registers, not DFLL registers. > Functions that operate on registers in one IP block shouldn't be located > in another IP block's driver. Paul & Co., These patches appear fine to me but I did not see any Acks, nor could I tell if a v2 was necessary based on the comments. Will there be another version? If not an Acked-by or Reviewed-by would be cool. Regards, Mike > > > - Paul