From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org"
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control
Date: Wed, 19 Jun 2013 11:45:42 +0300 [thread overview]
Message-ID: <20130619084542.GB3847@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <20130607121901.21868.65416.stgit-orwA252wQtA@public.gmane.org>
On Fri, Jun 07, 2013 at 02:19:09PM +0200, Paul Walmsley wrote:
> Add DFLL DVCO reset line control functions to the CAR IP block driver.
>
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block. This reset line is asserted upon SoC
> reset. Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
>
> Thanks to Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying this and
> saving hours of debugging time.
>
> Signed-off-by: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Cc: Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Cc: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Reviewed-by: <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cheers,
Peter.
prev parent reply other threads:[~2013-06-19 8:45 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-07 12:18 [PATCH 0/3] clk: tegra: T114: add DFLL prerequisites Paul Walmsley
[not found] ` <20130607121505.21868.72360.stgit-orwA252wQtA@public.gmane.org>
2013-06-07 12:18 ` [PATCH 1/3] clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL Paul Walmsley
2013-06-07 12:19 ` [PATCH 2/3] clk: tegra: T114: add DFLL source clocks Paul Walmsley
[not found] ` <20130607121858.21868.73882.stgit-orwA252wQtA@public.gmane.org>
2013-06-07 16:53 ` Stephen Warren
2013-06-07 12:19 ` [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control Paul Walmsley
[not found] ` <20130607121901.21868.65416.stgit-orwA252wQtA@public.gmane.org>
2013-06-07 16:57 ` Stephen Warren
[not found] ` <51B21105.1080301-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-06-07 17:06 ` Paul Walmsley
[not found] ` <alpine.DEB.2.02.1306071703050.7753-rwI8Ez+7Ko+d5PgPZx9QOdBPR1lH4CV8@public.gmane.org>
2013-06-11 7:31 ` Prashant Gaikwad
2013-06-11 9:47 ` Paul Walmsley
[not found] ` <alpine.DEB.2.02.1306110944130.22645-rwI8Ez+7Ko+d5PgPZx9QOdBPR1lH4CV8@public.gmane.org>
2013-06-16 4:22 ` Mike Turquette
2013-06-17 20:22 ` Paul Walmsley
[not found] ` <alpine.DEB.2.02.1306172019270.17176-rwI8Ez+7Ko+d5PgPZx9QOdBPR1lH4CV8@public.gmane.org>
2013-06-18 18:28 ` Mike Turquette
2013-06-18 18:33 ` Paul Walmsley
2013-06-19 8:45 ` Peter De Schrijver [this message]
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