Re: [PATCH] ARM: tegra: Fix Beaver's PCIe lane configuration

[Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

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On Fri, Jun 21, 2013 at 02:23:52PM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
> than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
> and the only way those align is with a x2 x2 x2 configuration.

Looking at the schematics again I have to agree. Thanks for catching
this.

> Also, disable root port 1; there's nothing connected to it. Root port 0
> is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.
> 
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This is to be applied to Thierry's WIP PCIe driver branch.

I've applied this to my tegra/next branch and will squash it into the
Beaver patch that's already there.

You mention another fix that might be required for PCIe on Tegra30
(additional write to the PADS_REFCLK_CFG1) register. Did that turn out
to fix communication of the third port?

Thierry

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