[PATCH] HACK: clk: tegra: Do not mark PLLE as fixed

[PATCH] HACK: clk: tegra: Do not mark PLLE as fixed

[Thierry Reding]

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra114.c | 2 --
 drivers/clk/tegra/clk-tegra124.c | 2 --
 drivers/clk/tegra/clk-tegra20.c  | 2 --
 drivers/clk/tegra/clk-tegra30.c  | 3 +--
 4 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 624077d..8f583dc 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -587,8 +587,6 @@ static struct tegra_clk_pll_params pll_e_params = {
 	.lock_delay = 300,
 	.div_nmp = &plle_nmp,
 	.freq_table = pll_e_freq_table,
-	.flags = TEGRA_PLL_FIXED,
-	.fixed_rate = 100000000,
 };
 
 static struct div_nmp pllre_nmp = {
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 266e80b..2f7361f 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -464,8 +464,6 @@ static struct tegra_clk_pll_params pll_e_params = {
 	.lock_delay = 300,
 	.div_nmp = &plle_nmp,
 	.freq_table = pll_e_freq_table,
-	.flags = TEGRA_PLL_FIXED,
-	.fixed_rate = 100000000,
 };
 
 static const struct clk_div_table pll_re_div_table[] = {
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 58faac5..e4d2071 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -427,8 +427,6 @@ static struct tegra_clk_pll_params pll_e_params = {
 	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 	.lock_delay = 0,
 	.freq_table = pll_e_freq_table,
-	.flags = TEGRA_PLL_FIXED,
-	.fixed_rate = 100000000,
 };
 
 static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 24ce357..69bf84d 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -577,8 +577,7 @@ static struct tegra_clk_pll_params pll_e_params = {
 	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 	.lock_delay = 300,
 	.freq_table = pll_e_freq_table,
-	.flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
-	.fixed_rate = 100000000,
+	.flags = TEGRA_PLLE_CONFIGURE,
 };
 
 static unsigned long tegra30_input_freq[] = {
-- 
1.8.4

Re: [PATCH] HACK: clk: tegra: Do not mark PLLE as fixed

[Stephen Warren]

On 10/29/2013 08:40 AM, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

What does this patch solve? A description would be nice.

I thought that this PLL essentially was fixed; while it may have some
registers than /can/ change the rate, hasn't the HW team only
characterized it to run at the single frequency that PCIe requires,
hence SW is supposed to treat it as fixed?

Re: [PATCH] HACK: clk: tegra: Do not mark PLLE as fixed

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 755 bytes --]

On Tue, Oct 29, 2013 at 01:41:58PM -0600, Stephen Warren wrote:
> On 10/29/2013 08:40 AM, Thierry Reding wrote:
> > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> What does this patch solve? A description would be nice.
> 
> I thought that this PLL essentially was fixed; while it may have some
> registers than /can/ change the rate, hasn't the HW team only
> characterized it to run at the single frequency that PCIe requires,
> hence SW is supposed to treat it as fixed?

Peter fixed it up properly. As indicated by the HACK: tag, this was
really only a workaround to make Dalmore boot again. PLLE didn't use to
be marked as fixed, which seems to be the reason why we've never seen
this.

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]