Re: [PATCH 3/3] clk: tegra: Properly setup PWM clock on Tegra30

[Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

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On Fri, Nov 01, 2013 at 06:47:09PM +0200, Peter De Schrijver wrote:
> > > 
> > > And also not validated. Also by policy PLLC2 and PLLC3 are used for scaling
> > > IP blocks. So I don't think it makes sense to use them for PWM?
> > 
> > But the policy is already defined in the clock initialization tables, so
> > we could still setup the clock to exhibit all the possible HW choices
> > and simply not use those excluded "by policy".
> > 
> 
> That's only the 'default'. Nothing prevents a driver from doing a
> clk_set_parent().

Well, I think this is one of the rare cases where it would even make
sense for the driver to impose policy. I would still rather see the
driver expose all possible hardware options and leave up any policy to
other code.

If you really feel strongly about not exposing PLLC2 and PLLC3, can we
at least have a comment in the driver describing why they aren't exposed
so that if people stumble over this again they know why?

Thierry

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