[PATCH 1/5] clk: tegra: fix blink clock rate

[PATCH 1/5] clk: tegra: fix blink clock rate

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The blink clock rate needs to be configured, or it will run at ~1Hz
rather than the desired 32KHz. If it runs at the wrong rate, e.g. the
SDIO WiFi on Seaboard and Cardhu will fail to be detected.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This probably needs to be squashed into commit 32721a734a3d "clk: tegra:
move PMC, fixed clocks to common files".
---
 drivers/clk/tegra/clk-tegra-pmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
index 00e8275a7178..08b21c1ee867 100644
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
 	}
 
 	/* blink */
+	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
 	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
 				pmc_base + PMC_DPD_PADS_ORIDE,
 				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
-- 
1.8.1.5

[PATCH 2/5] clk: tegra: remove some redundant defines from Tegra114

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

These #defines aren't used. Delete them.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This probably should be squashed into commit 32721a734a3d "clk: tegra:
move PMC, fixed clocks to common files".
---
 drivers/clk/tegra/clk-tegra114.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9036a22ee5aa..70bfefebcca5 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -107,13 +107,6 @@
 #define PLLC_OUT 0x84
 #define PLLM_OUT 0x94
 
-#define PMC_CLK_OUT_CNTRL 0x1a8
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_CTRL 0
-#define PMC_CTRL_BLINK_ENB 7
-#define PMC_BLINK_TIMER 0x40
-
 #define OSC_CTRL			0x50
 #define OSC_CTRL_OSC_FREQ_SHIFT		28
 #define OSC_CTRL_PLL_REF_DIV_SHIFT	26
-- 
1.8.1.5

[PATCH 3/5] clk: tegra: remove some redundant defines from Tegra30

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

These #defines aren't used. Delete them.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This probably should be squashed into commit ba2e2e8f2c55 "clk: tegra:
move tegra30 to common infra".
---
 drivers/clk/tegra/clk-tegra30.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 51c093c96657..92c46f1fb5d1 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -118,13 +118,6 @@
 
 #define AUDIO_SYNC_DOUBLER 0x49c
 
-#define PMC_CTRL 0
-#define PMC_CTRL_BLINK_ENB 7
-
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_BLINK_TIMER 0x40
-
 #define UTMIP_PLL_CFG2 0x488
 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
-- 
1.8.1.5

[PATCH 4/5] clk: tegra: remove some redunant defines from Tegra20

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

These #defines aren't used. Delete them.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This probably should be squashed into commit 776b2c0ba0dd "clk: tegra:
move tegra20 to common infra".
---
 drivers/clk/tegra/clk-tegra20.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 58faac5f509e..be5bdbab78a6 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -118,12 +118,6 @@
 
 #define AUDIO_SYNC_CLK 0x38
 
-#define PMC_CTRL 0x0
-#define PMC_CTRL_BLINK_ENB 7
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_BLINK_TIMER 0x40
-
 /* Tegra CPU clock and reset control regs */
 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
-- 
1.8.1.5

[PATCH 5/5] clk: tegra: remove some redundant defines from Tegra124

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

These #defines aren't used. Delete them.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This probably should be squashed into commit 8a0fc8917eef "clk: tegra124:
Add support for Tegra124 clocks".
---
 drivers/clk/tegra/clk-tegra124.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 266e80b51d38..623fbf35ee08 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -84,8 +84,6 @@
 
 #define PLLXC_SW_MAX_P 6
 
-#define PMC_BLINK_TIMER 0x40
-
 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 
-- 
1.8.1.5

Re: [PATCH 1/5] clk: tegra: fix blink clock rate

[Peter De Schrijver]

On Thu, Nov 21, 2013 at 12:47:18AM +0100, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> The blink clock rate needs to be configured, or it will run at ~1Hz
> rather than the desired 32KHz. If it runs at the wrong rate, e.g. the
> SDIO WiFi on Seaboard and Cardhu will fail to be detected.
> 
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This probably needs to be squashed into commit 32721a734a3d "clk: tegra:
> move PMC, fixed clocks to common files".
> ---

Acked-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

I will squash this into the mentioned commit.

Cheers,

Peter.

Re: [PATCH 1/5] clk: tegra: fix blink clock rate

[Thierry Reding]

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On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> The blink clock rate needs to be configured, or it will run at ~1Hz
> rather than the desired 32KHz. If it runs at the wrong rate, e.g. the
> SDIO WiFi on Seaboard and Cardhu will fail to be detected.

How is this related to WiFi?

> 
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This probably needs to be squashed into commit 32721a734a3d "clk: tegra:
> move PMC, fixed clocks to common files".
> ---
>  drivers/clk/tegra/clk-tegra-pmc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
> index 00e8275a7178..08b21c1ee867 100644
> --- a/drivers/clk/tegra/clk-tegra-pmc.c
> +++ b/drivers/clk/tegra/clk-tegra-pmc.c
> @@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
>  	}
>  
>  	/* blink */
> +	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
>  	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
>  				pmc_base + PMC_DPD_PADS_ORIDE,
>  				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);

Perhaps a better location would be a few lines below, where the "blink"
clock is registered, since this actually controls the "blink" clock
rather than "blink_override". But either way:

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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Re: [PATCH 1/5] clk: tegra: fix blink clock rate

[Thierry Reding]

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On Fri, Nov 29, 2013 at 04:22:42PM +0100, Thierry Reding wrote:
> On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
> > From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > 
> > The blink clock rate needs to be configured, or it will run at ~1Hz
> > rather than the desired 32KHz. If it runs at the wrong rate, e.g. the
> > SDIO WiFi on Seaboard and Cardhu will fail to be detected.
> 
> How is this related to WiFi?
> 
> > 
> > Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > ---
> > This probably needs to be squashed into commit 32721a734a3d "clk: tegra:
> > move PMC, fixed clocks to common files".
> > ---
> >  drivers/clk/tegra/clk-tegra-pmc.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
> > index 00e8275a7178..08b21c1ee867 100644
> > --- a/drivers/clk/tegra/clk-tegra-pmc.c
> > +++ b/drivers/clk/tegra/clk-tegra-pmc.c
> > @@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
> >  	}
> >  
> >  	/* blink */
> > +	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
> >  	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
> >  				pmc_base + PMC_DPD_PADS_ORIDE,
> >  				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
> 
> Perhaps a better location would be a few lines below, where the "blink"
> clock is registered, since this actually controls the "blink" clock
> rather than "blink_override". But either way:

Just realized that Peter already squashed all of these into his -next
branch, so nevermind.

Thierry

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Re: [PATCH 1/5] clk: tegra: fix blink clock rate

[Stephen Warren]

On 11/29/2013 08:22 AM, Thierry Reding wrote:
> On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> 
>> The blink clock rate needs to be configured, or it will run at
>> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate,
>> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be
>> detected.
> 
> How is this related to WiFi?

The "blink" clock output from Tegra is connected to the WiFi module,
which then uses it for something; it probably has a PLL connected to
it that drives all the internal circuitry.

Re: [PATCH 1/5] clk: tegra: fix blink clock rate

[Thierry Reding]

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On Sun, Dec 01, 2013 at 12:21:17PM -0700, Stephen Warren wrote:
> On 11/29/2013 08:22 AM, Thierry Reding wrote:
> > On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote:
> >> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >> 
> >> The blink clock rate needs to be configured, or it will run at
> >> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate,
> >> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be
> >> detected.
> > 
> > How is this related to WiFi?
> 
> The "blink" clock output from Tegra is connected to the WiFi module,
> which then uses it for something; it probably has a PLL connected to
> it that drives all the internal circuitry.

Okay, thanks for explaining.

Thierry

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