Re: [PATCHv8 15/21] iommu/tegra124: smmu: add support platform data

[Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

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On Fri, May 30, 2014 at 07:39:01PM +0300, Hiroshi Doyu wrote:
> 
> Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> writes:
> 
> > On 05/30/2014 05:20 AM, Hiroshi Doyu wrote:
> >> The later Tegra SoC(>= T124) has more registers for
> >> MC_SMMU_TRANSLATION_ENABLE_*. Now those info is provided as platfrom
> >> data. If those varies a lot on SoCs in the future, we can consider
> >> putting them into DT later.
> >
> >> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt
> >
> >>  Required properties:
> >> -- compatible : "nvidia,tegra30-smmu"
> >> -- reg : Should contain 3 register banks(address and length) for each
> >> +- compatible : "nvidia,tegra124-smmu", "nvidia,tegra30-smmu"
> >> +- reg : Can contain multiple register banks(address and length) for each
> >>    of the SMMU register blocks.
> >
> > How many is "multiple"? This seems like rather a weak definition of how
> > many entries are expected. What are the different register banks?
> 
> SMMU registers are part of MC registers. SMMU registeres are interleaved
> by MC(non-SMMU) registeres, most likely it's about ~10 banks.
> 
> We concluded to not have SMMU as a child of MC since their features are
> so independent long time ago. This interleaved register locations are
> not so good. I requested H/W team to have them completely separated, but
> itt was too late to change.

This situation is really messy. In my opinion we should break DT
compatibility and expose this through a single memory-controller driver
rather than split it up into different subdevices.

That reflects the hardware more accurately and gets rid of a number of
quirks currently required just to make things work.

Thierry

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