From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
marcheu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org
Subject: Re: [PATCH 3/4] host1x: mipi: Include clock lanes in mipi calibrate
Date: Thu, 7 Aug 2014 10:34:30 +0200 [thread overview]
Message-ID: <20140807083429.GA13315@ulmo.nvidia.com> (raw)
In-Reply-To: <1407391907-19488-4-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
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On Thu, Aug 07, 2014 at 02:11:46AM -0400, Sean Paul wrote:
> When calibrating the mipi phy, also include the clock lanes
> in the calibration.
>
> Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> drivers/gpu/host1x/mipi.c | 70 +++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 56 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
> index 0af2892..80578dc 100644
> --- a/drivers/gpu/host1x/mipi.c
> +++ b/drivers/gpu/host1x/mipi.c
> @@ -49,10 +49,18 @@
> #define MIPI_CAL_CONFIG_DSIC 0x10
> #define MIPI_CAL_CONFIG_DSID 0x11
>
> +#define MIPI_CAL_CONFIG_DSIAB_CLK 0x19
> +#define MIPI_CAL_CONFIG_DSICD_CLK 0x1a
> +#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
> +#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
> +#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
> +
These registers don't seem to exist on Tegra114 and earlier. It also
seems like MIPI_CAL_CONFIG_DSIC and MIPI_CAL_CONFIG_DSID no longer exist
on Tegra124 and later. And CSIC and CSID seem to be shared with DSIB
(channel A and B) now.
So I think we'll need something more elaborate than this. It should be
differentiating between SoC revisions to allow checking for valid pad
selection when calibrating.
I'll see if I can find out what's up with the change between Tegra114
and Tegra124 regarding the DSIC and DSID pads. It looks to me like they
were merged to match the DSIA and DSIB controllers, whereas before DSIA
and DSIB were used for controller DSIA and DSIC and DSID were used for
controller DSIB.
Thierry
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next prev parent reply other threads:[~2014-08-07 8:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-07 6:11 [PATCH 0/4] host1x: mipi: Some patches to improve d-phy calibration Sean Paul
[not found] ` <1407391907-19488-1-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-07 6:11 ` [PATCH 1/4] host1x: mipi: Add new parent clock for mipi calibration Sean Paul
[not found] ` <1407391907-19488-2-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-07 8:11 ` Thierry Reding
2014-08-07 14:15 ` Sean Paul
[not found] ` <CAOw6vbKiECG8w6V3zvnr5Z4r4WuRsq556gtspAnM7Drj=A8m8A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-07 14:52 ` Thierry Reding
2014-08-07 6:11 ` [PATCH 2/4] host1x: mipi: Preserve the contents of MIPI_CAL_CTRL Sean Paul
[not found] ` <1407391907-19488-3-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-07 8:12 ` Thierry Reding
2014-08-07 6:11 ` [PATCH 3/4] host1x: mipi: Include clock lanes in mipi calibrate Sean Paul
[not found] ` <1407391907-19488-4-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-07 8:34 ` Thierry Reding [this message]
[not found] ` <20140807083429.GA13315-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2014-08-07 17:14 ` Sean Paul
[not found] ` <CAOw6vbJw8S477S+7L_+ozF2aoxUw+TT7=KQObTz6HYXpzPhr5Q@mail.gmail.com>
[not found] ` <CAOw6vbJw8S477S+7L_+ozF2aoxUw+TT7=KQObTz6HYXpzPhr5Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-25 6:33 ` Thierry Reding
2014-08-07 6:11 ` [PATCH 4/4] host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register Sean Paul
[not found] ` <1407391907-19488-5-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-08-07 8:39 ` Thierry Reding
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