From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter De Schrijver Subject: Re: [PATCH] ARM: tegra: Use PMC scratch register 40 for tegra_resume() location store Date: Fri, 9 Jan 2015 12:29:22 +0200 Message-ID: <20150109102922.GC10073@tbergstrom-lnx.Nvidia.com> References: <1419202392-1159-1-git-send-email-digetx@gmail.com> <54984429.8040905@wwwdotorg.org> <5498549B.8070101@gmail.com> <54985C30.7020605@wwwdotorg.org> <20150108105742.GI1987@ulmo.nvidia.com> <20150108123709.GX10073@tbergstrom-lnx.Nvidia.com> <20150109095134.GC27845@ulmo> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <20150109095134.GC27845@ulmo> Sender: stable-owner@vger.kernel.org To: Thierry Reding Cc: Stephen Warren , linux-arm-kernel@lists.infradead.org, Alexandre Courbot , Russell King , Stefano Stabellini , Sekhar Nori , linux-kernel@vger.kernel.org, Haojian Zhuang , stable@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Dmitry Osipenko , Shawn Guo , Christoffer Dall List-Id: linux-tegra@vger.kernel.org On Fri, Jan 09, 2015 at 10:51:35AM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key >=20 > On Thu, Jan 08, 2015 at 02:37:09PM +0200, Peter De Schrijver wrote: > > On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote: > > > > Old Signed by an unknown key > > >=20 > > > On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote: > > > > On 12/22/2014 10:27 AM, Dmitry Osipenko wrote: > > > > >22.12.2014 19:17, Stephen Warren =D0=BF=D0=B8=D1=88=D0=B5=D1=82= : > > > > >>On 12/21/2014 03:52 PM, Dmitry Osipenko wrote: > > > > >>>Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") = changed > > > > >>>tegra_resume() > > > > >>>location storing from late to early and as result broke susp= end on tegra20. > > > > >>>PMC scratch register 41 was used by tegra lp1 suspend core c= ode for storing > > > > >>>physical memory address of common resume function and in the= same time used by > > > > >>>tegra20 cpuidle driver for storing cpu1 "resettable" status,= so it implied > > > > >>>strict order of scratch register use. Fix it by using scratc= h 40 instead of 41 > > > > >>>for tegra_resume() location store. > > > > >> > > > > >>You likely can't simply change the PMC scratch register usage= arbitrarily; > > > > >>specific registers are designated for specific purposes, and = code outside the > > > > >>Linux kernel (bootloaders, LP0 resume code, secure monitors, = etc.) may depend on > > > > >>those specific values being in those registers. Without signi= ficant research, > > > > >>I'd suggest not changing the PMC scratch register usage. > > > > > > > > > >Sure, that's why I asked to verify if scratch register 40 is i= n use in the > > > > >comment after commit message. > > > >=20 > > > > Sorry, I didn't notice that. > > > >=20 > > > > >I've checked that u-boot doesn't use it (since > > > > >upstream kernel doesn't care about any other bootloader), but = no idea about > > > > >secure monitor. It's definitely safer to avoid changing scratc= h regs usage, I > > > > >thought that proposed solution would be best from the pure cod= e point of view. > > > > >So, I'm considering your answer as a rejection of the patch (p= lease, let me know > > > > >if I'm wrong) and will prepare another one. Btw, it would be n= ice to have > > > > >scratch registers usage publicly documented somewhere (on "Teg= ra Public > > > > >Application Notes" webpage for example), if it's possible, of = course. > > > >=20 > > > > At this stage in Tegra20 development, I think it'd be best to a= void changing > > > > any scratch register usage if at all possible. > > >=20 > > > Sorry, I had completely missed this discussion. When looking at t= he code > > > it doesn't look like this particular "resettable" status needs to= be > > > stored in a PMC scratch register. It can't be stored in RAM becau= se that > > > goes into self-refresh as part of LP1, but how about just putting= it > > > into IRAM? That stays on in both LP1 and LP2, so should be suitab= le for > > > this use-case. It would make the code slightly more complex but u= sing a > > > single scratch register for multiple purposes sounds brittle and = easy to > > > break (as evidenced by the offending commit). > > >=20 > > > Otherwise it would seem that PMC_SCRATCH40 is only used to store = EMC > > > configuration data across LP0 suspend/resume, so I wouldn't think= it'd > > > cause problems if we used that instead of PMC_SCRATCH41 to store = the > > > "resettable" state. > > >=20 > >=20 > > No. Usually the scratch registers for EMC config data are setup onc= e by the > > bootloader and never touched by the kernel after that. So I would n= ot > > recommend reusing those registers for different purposes. >=20 > Right, I misread the code in the downstream kernel. Though it's not t= he > bootloader that does it (at least on Tegra20), but some early code in > the kernel. >=20 > IRAM sounds like a good candidate still. Or do you know of anything t= hat > would exclude IRAM as storage location for this data? No. I can't think of a reason this flag could not be in IRAM. Cheers, Peter.