Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource

Peter De Schrijver
2015-02-12T13:54:40Z

On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
>
> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> and also provides automatic CPU rail voltage scaling as well. The DFLL
> is a separate IP block from the usual Tegra124 clock-and-reset
> controller, so it gets its own node in the device tree.
>

Please add devicetree@vger.kernel.org to the next CC list.

Peter.