From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Benson Leung <bleung@chromium.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 08/20] clk: tegra: pll: Add logic for handling SDM data
Date: Wed, 6 May 2015 15:57:20 +0200 [thread overview]
Message-ID: <20150506135719.GB22098@ulmo.nvidia.com> (raw)
In-Reply-To: <554916F8.2060908@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 2784 bytes --]
On Tue, May 05, 2015 at 03:16:08PM -0400, Rhyland Klein wrote:
> On 5/4/2015 7:01 PM, Benson Leung wrote:
> > On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@nvidia.com> wrote:
> >> @@ -495,6 +505,28 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> >> return 0;
> >> }
> >>
> >> +static void clk_pll_set_sdm_data(struct clk_hw *hw,
> >> + struct tegra_clk_pll_freq_table *cfg)
> >> +{
> >> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> >> + u32 val;
> >> +
> >> + if (!pll->params->sdm_din_reg)
> >> + return;
> >> +
> >> + if (cfg->sdm_data) {
> >> + val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
> >> + val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
> >> + pll_writel_sdm_din(val, pll);
> >> + }
> >> +
> >> + val = pll_readl_sdm_ctrl(pll);
> >> + if (!cfg->sdm_data != !(val & pll->params->sdm_ctrl_en_mask)) {
> >
> > You can use sdm_en_mask(pll) here.
> >
> > I'm not super clear about what you're trying to accomplish here with
> > !cfg->sdm_data != !(val & mask).
> > Are you just checking if the masked value is different from sdm_data,
> > but accounting for the integer widths being different (u16 vs u32)?
>
> So I got clarification from the downstream author to be sure, and this
> is the answer to what this is checking:
>
> (<Configuration has non zero SDM_DATA> AND <sdm control is disabled>)
> OR
> (<Configuration has zero SDM_DATA> AND <sdm control is enabled>)
>
> So the check is correct, just a complicated way of expressing it.
Can it be rewritten to be less complicated? I hate it when I have to
look at code for several seconds and still not understand what it's
doing. Why not something that is closer to the pseudo code you gave:
bool enabled = (val & pll->params->sdm_ctrl_en_mask) != 0;
if ((enabled && cfg->sdm_data == 0) || (!enabled && cfg->sdm_data != 0))
? Also I think this could use some could comments explaining what's
going on. Perhaps this could be simplified even further:
if (cfg->sdm_data == 0 && enabled)
val &= ~pll->params->sdm_ctrl_en_mask;
if (cfg->sdm_data != 0 && !enabled)
val |= pll->params->sdm_ctrl_en_mask;
pll_writel_sdm_ctrl(val, pll);
Now that I have a /much/ easier time reading and understanding. That may
not even require comments because it's pretty plain what's going on. But
there may be some advantage in adding comments about SDM in general. The
comment could be something like what you have in the commit message, so
that people don't have to go find the commit that added the code to find
out what this is doing.
Thierry
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next prev parent reply other threads:[~2015-05-06 13:57 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-04 16:37 [PATCH v4 00/20] Tegra210 Clock Support Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 05/20] clk: tegra: pll: update warning msg Rhyland Klein
[not found] ` <1430757460-9478-6-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 20:20 ` Benson Leung
[not found] ` <1430757460-9478-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 16:37 ` [PATCH v4 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
[not found] ` <1430757460-9478-2-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 18:05 ` Benson Leung
2015-05-07 15:15 ` Thierry Reding
[not found] ` <20150507151545.GB25866-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-05-07 15:49 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
[not found] ` <1430757460-9478-3-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 19:45 ` Benson Leung
[not found] ` <CANLzEkuxPMX2+rq4EkCs6iV4=qRK69u=Ezgy4Zn_KsSh1+oEfA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 20:14 ` Rhyland Klein
2015-05-06 13:59 ` Thierry Reding
2015-05-06 16:24 ` Rhyland Klein
2015-05-04 21:19 ` Andrew Bresticker
2015-05-06 11:20 ` Jim Lin
2015-05-06 14:15 ` Thierry Reding
2015-05-06 16:20 ` Rhyland Klein
2015-05-06 14:12 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 03/20] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 04/20] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-04 20:11 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
[not found] ` <1430757460-9478-7-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 20:35 ` Benson Leung
[not found] ` <CANLzEksajPjf1VH8Zn-1oXhgL8f-b7GuCBprExTP-w18WbCC4A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-06 14:18 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 08/20] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
[not found] ` <1430757460-9478-9-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:01 ` Benson Leung
[not found] ` <CANLzEksFVpYOtcG5QHHfQa6bGXJ6nMYrsP4yG=5wszxCHrWqug-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 19:16 ` Rhyland Klein
2015-05-06 13:57 ` Thierry Reding [this message]
2015-05-06 16:16 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 09/20] clk: tegra: pll: Add logic for SS Rhyland Klein
[not found] ` <1430757460-9478-10-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:11 ` Benson Leung
2015-05-05 20:15 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-05 17:15 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 12/20] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-07 15:11 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 14/20] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 16/20] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 17/20] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 18/20] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 19/20] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-06 14:51 ` Thierry Reding
[not found] ` <20150506145113.GH22098-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-05-06 16:18 ` Rhyland Klein
2015-05-06 17:21 ` Rhyland Klein
[not found] ` <554A4D82.80307-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-07 15:16 ` Thierry Reding
2015-05-07 10:39 ` Jim Lin
[not found] ` <554B40D7.3040207-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-07 16:07 ` Rhyland Klein
2015-05-07 15:18 ` Thierry Reding
2015-05-05 13:14 ` [PATCH v4 00/20] Tegra210 Clock Support Thierry Reding
2015-05-05 15:55 ` Rhyland Klein
2015-05-06 13:37 ` Thierry Reding
2015-05-06 16:10 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 07/20] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
[not found] ` <1430757460-9478-8-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 21:42 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
[not found] ` <1430757460-9478-11-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-04 23:34 ` Benson Leung
[not found] ` <CANLzEktX3tiBXvxKgToUr5S7xZ+YibpeG6tDvW1R=qkW6_T5WQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-05 19:55 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 13/20] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 15/20] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 20/20] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
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