Re: [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6

[Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

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On Mon, May 04, 2015 at 01:35:09PM -0700, Benson Leung wrote:
> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >
> > New SoC's may have more then 3 MISC registers, so bump up the
> > array size and use a #define to be more informative about the value.
> >
> > Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > ---
> >  drivers/clk/tegra/clk.h |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> > index 5759b8bfb80e..8e7361886cf9 100644
> > --- a/drivers/clk/tegra/clk.h
> > +++ b/drivers/clk/tegra/clk.h
> > @@ -156,6 +156,8 @@ struct div_nmp {
> >         u8              override_divp_shift;
> >  };
> >
> > +#define MAX_PLL_MISC_REG_COUNT 6
> > +
> >  /**
> >   * struct clk_pll_params - PLL parameters
> >   *
> > @@ -213,7 +215,7 @@ struct tegra_clk_pll_params {
> >         u32             iddq_bit_idx;
> >         u32             aux_reg;
> >         u32             dyn_ramp_reg;
> > -       u32             ext_misc_reg[3];
> > +       u32             ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
> >         u32             pmc_divnm_reg;
> >         u32             pmc_divp_reg;
> >         u32             flags;
> 
> 
> Missing kernel doc above for ext_misc_reg and some other surrounding members.

I added the missing kerneldoc in that patch I sent out earlier. The
problem is preexisting for this field, so doing it in a separate patch
is fine in my opinion.

Thierry

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