From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH] ARM: v7 setup function should invalidate L1 cache Date: Thu, 21 May 2015 10:08:42 +0800 Message-ID: <20150521020841.GL24844@dragon> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Russell King Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Christian Daudt , Florian Fainelli , Marc Carino , Brian Norris , Gregory Fong , Sebastian Hesselbarth , Wei Xu , Sascha Hauer , Jason Cooper , Andrew Lunn , Gregory Clement , Barry Song , Heiko Stuebner , Simon Horman , Magnus Damm , Dinh Nguyen , Stephen Warren , Thierry Reding , Alexandre Courbot List-Id: linux-tegra@vger.kernel.org On Tue, May 19, 2015 at 05:12:56PM +0100, Russell King wrote: > All ARMv5 and older CPUs invalidate their caches in the early assembly > setup function, prior to enabling the MMU. This is because the L1 > cache should not contain any data relevant to the execution of the > kernel at this point; all data should have been flushed out to memory. > > This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, > these typically do not search their caches when caching is disabled (as > it needs to be when the MMU is disabled) so this change should be safe. > > ARMv7 allows there to be CPUs which search their caches while caching is > disabled, and it's permitted that the cache is uninitialised at boot; > for these, the architecture reference manual requires that an > implementation specific code sequence is used immediately after reset > to ensure that the cache is placed into a sane state. Such > functionality is definitely outside the remit of the Linux kernel, and > must be done by the SoC's firmware before _any_ CPU gets to the Linux > kernel. > > Changing the data cache clean+invalidate to a mere invalidate allows us > to get rid of a lot of platform specific hacks around this issue for > their secondary CPU bringup paths - some of which were buggy. > > Signed-off-by: Russell King > --- ... > arch/arm/mach-imx/headsmp.S | 1 - Acked-by: Shawn Guo