From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
Bill Huang <bilhuang@nvidia.com>, Jim Lin <jilin@nvidia.com>,
Benson Leung <bleung@chromium.org>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, Mark Kuo <mkuo@nvidia.com>
Subject: Re: [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config
Date: Wed, 13 Jan 2016 15:00:13 +0100 [thread overview]
Message-ID: <20160113140013.GA15782@ulmo> (raw)
In-Reply-To: <1452278714-10751-9-git-send-email-rklein@nvidia.com>
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On Fri, Jan 08, 2016 at 01:45:13PM -0500, Rhyland Klein wrote:
> From: Mark Kuo <mkuo@nvidia.com>
>
> Fix PLLE spread spectrum configuration so it aligns with downstream
> kernel.
>
> Signed-off-by: Mark Kuo <mkuo@nvidia.com>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
Can we have a better description for this. Merely saying that this is
meant to align things with downstream isn't really helpful for anyone
who doesn't have the downstream kernel to check against.
I also see some potential for splitting this up into several logical
changes, since for example it seems to fix a typo (?) where some bits
were being set that should really be cleared, and in other hunks it
splits up the SS coefficients by SoC generation. Splitting it up into
logical changes might make it easier to write accurate commit
descriptions rather than this kind of blanket commit message.
Thierry
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next prev parent reply other threads:[~2016-01-13 14:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-08 18:45 [PATCH 0/9 REPOST] Tegra CLK Fixes Rhyland Klein
2016-01-08 18:45 ` [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein
2016-01-08 18:45 ` [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein
[not found] ` <1452278714-10751-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-08 18:45 ` [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein
2016-01-08 18:45 ` [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein
2016-01-08 18:45 ` [PATCH 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein
2016-01-08 18:45 ` [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein
2016-01-08 18:45 ` [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein
2016-01-08 18:45 ` [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein
2016-01-13 14:00 ` Thierry Reding [this message]
2016-01-08 18:45 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
[not found] ` <1452278714-10751-10-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 14:03 ` Thierry Reding
2016-01-13 16:27 ` Rhyland Klein
[not found] ` <56967ADD.8090904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 17:28 ` Thierry Reding
2016-01-13 14:05 ` [PATCH 0/9 REPOST] Tegra CLK Fixes Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2016-01-08 18:37 Rhyland Klein
2016-01-08 18:37 ` [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein
2015-12-10 22:08 [PATCH 0/9] Tegra CLK Fixes Rhyland Klein
2015-12-10 22:08 ` [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein
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