From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Jim Lin <jilin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate
Date: Wed, 13 Jan 2016 15:03:09 +0100 [thread overview]
Message-ID: <20160113140309.GB15782@ulmo> (raw)
In-Reply-To: <1452278714-10751-10-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On Fri, Jan 08, 2016 at 01:45:14PM -0500, Rhyland Klein wrote:
> Initialize PLL_D2 to a sane rate at the start of the day.
>
> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 1 +
> 1 file changed, 1 insertion(+)
There are a lot of assumptions in this commit message. I'm asking myself
why does it need to be initialized to any rate at all? Isn't it up to
the user driver to set the PLL to whatever it knows to be a sane rate?
Why is 594 MHz a sane rate?
A good commit message should answer those questions.
Thierry
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next prev parent reply other threads:[~2016-01-13 14:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-08 18:45 [PATCH 0/9 REPOST] Tegra CLK Fixes Rhyland Klein
2016-01-08 18:45 ` [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein
2016-01-08 18:45 ` [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein
[not found] ` <1452278714-10751-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-08 18:45 ` [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein
2016-01-08 18:45 ` [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein
2016-01-08 18:45 ` [PATCH 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein
2016-01-08 18:45 ` [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein
2016-01-08 18:45 ` [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein
2016-01-08 18:45 ` [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein
2016-01-13 14:00 ` Thierry Reding
2016-01-08 18:45 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
[not found] ` <1452278714-10751-10-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 14:03 ` Thierry Reding [this message]
2016-01-13 16:27 ` Rhyland Klein
[not found] ` <56967ADD.8090904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 17:28 ` Thierry Reding
2016-01-13 14:05 ` [PATCH 0/9 REPOST] Tegra CLK Fixes Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2016-01-08 18:37 Rhyland Klein
2016-01-08 18:37 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
2015-12-10 22:08 [PATCH 0/9] Tegra CLK Fixes Rhyland Klein
2015-12-10 22:08 ` [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein
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