From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding@gmail.com>
Subject: Re: [Patch V2 9/9] clk: tegra: pll: Fix PLLE SS coefficients val
Date: Mon, 25 Jan 2016 13:49:12 +0100
Message-ID: <20160125124912.GN20452@ulmo.nvidia.com>
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To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>, Mike Turquette <mturquette@baylibre.com>, Stephen Warren <swarren@wwwdotorg.org>, Stephen Boyd <sboyd@codeaurora.org>, Alexandre Courbot <gnurou@gmail.com>, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Kuo <mkuo@nvidia.com>
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On Thu, Jan 14, 2016 at 02:26:42PM -0500, Rhyland Klein wrote:
> From: Mark Kuo <mkuo@nvidia.com>
>=20
> The PLLE_SS_COEFFICIENTS_VAL should be different for Tegra210
> from Tegra114. Add SoC generation specific versions for Tegra114
> and Tegra210 and use those in their respective plle_enable functions.
>=20
> Signed-off-by: Mark Kuo <mkuo@nvidia.com>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk-pll.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)

Applied, thanks.

Thierry

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