[PATCH] clk: tegra: Fix divider settings for Tegra210 pll_a

[PATCH] clk: tegra: Fix divider settings for Tegra210 pll_a

[Jon Hunter]

When setting the pll_a frequency, to what should be 368639844 Hz, the
actual output frequency of the pll is 737279687 Hz (as reported by the
debugfs clk_summary entry), which is double the expect frequency. The
calculations for the pll frequency appear to be correct and the problem
is caused by incorrect divider settings for the pll_a in the look-up
table of multipliers and dividers. The P dividers for all entries in the
table are all one less than they should be. Fix this by increasing the
value of the P dividers by 1 to get the expected rates.

The rates in the table have been verified using the following equations:

1. Integer NDIV (SDM_DIN = 0)
   fout = (fref * n) / (m * p)

2. Fractional NDIV
   fout = (fref * (n + 0.5 + (SDM_DIN/8192))) / (m * p)

Where SDM_DIN is a signed 16-bit value between 0xf000 and 0x1000.

Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---

Thierry, Rhyland, please note that after this change, the pll_a settings
match those in the nvidia downstream 3.18 kernel for Tegra210.

 drivers/clk/tegra/clk-tegra210.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 637041fd53ad..5e0652d4876b 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1761,15 +1761,15 @@ static struct div_nmp plla_nmp = {
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-	{ 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
-	{ 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
-	{ 12000000, 240000000, 60, 1, 2, 1,      0 },
-	{ 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
-	{ 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
-	{ 13000000, 240000000, 55, 1, 2, 1,      0 }, /* actual: 238.3 MHz */
-	{ 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
-	{ 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
-	{ 38400000, 240000000, 75, 3, 3, 1,      0 },
+	{ 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
+	{ 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
+	{ 12000000, 240000000, 60, 1, 3, 1,      0 },
+	{ 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
+	{ 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
+	{ 13000000, 240000000, 55, 1, 3, 1,      0 }, /* actual: 238.3 MHz */
+	{ 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
+	{ 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
+	{ 38400000, 240000000, 75, 3, 4, 1,      0 },
 	{        0,         0,  0, 0, 0, 0,      0 },
 };
 
-- 
2.1.4

Re: [PATCH] clk: tegra: Fix divider settings for Tegra210 pll_a

[Rhyland Klein]

On 2/5/2016 9:01 AM, Jon Hunter wrote:
> When setting the pll_a frequency, to what should be 368639844 Hz, the
> actual output frequency of the pll is 737279687 Hz (as reported by the
> debugfs clk_summary entry), which is double the expect frequency. The
> calculations for the pll frequency appear to be correct and the problem
> is caused by incorrect divider settings for the pll_a in the look-up
> table of multipliers and dividers. The P dividers for all entries in the
> table are all one less than they should be. Fix this by increasing the
> value of the P dividers by 1 to get the expected rates.
> 
> The rates in the table have been verified using the following equations:
> 
> 1. Integer NDIV (SDM_DIN = 0)
>    fout = (fref * n) / (m * p)
> 
> 2. Fractional NDIV
>    fout = (fref * (n + 0.5 + (SDM_DIN/8192))) / (m * p)
> 
> Where SDM_DIN is a signed 16-bit value between 0xf000 and 0x1000.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> 
> Thierry, Rhyland, please note that after this change, the pll_a settings
> match those in the nvidia downstream 3.18 kernel for Tegra210.
> 
>

This was an issue we had before/around merging T210 driver. The tegra
clock code was inconsistent in how it treated the pdiv. In some places
it stored the direct HW value in the frequency table entry struct (like
in the predefined frequencies like what you changed). Some places stored
the translated (=_hw_to_p_div()). This is most commonly a difference in
a factor of 2.

I found when initially doing the T210 that most clocks I requested rates
for came out at either 1/2 or 2x what I wanted depending on the path.

I think when Thierry merged my series, he added some code to address
this issue, as he saw it too I think. Depending on what his change was
(to consistently store either pdiv or hw_val) then we may need to adjust
ALL the predefined rates in the clk-tegra210 code.

Thierry, do you remember off-hand what you changed for that?

-rhyland

-- 
nvpublic

Re: [PATCH] clk: tegra: Fix divider settings for Tegra210 pll_a

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2749 bytes --]

On Fri, Feb 05, 2016 at 11:03:04AM -0500, Rhyland Klein wrote:
> On 2/5/2016 9:01 AM, Jon Hunter wrote:
> > When setting the pll_a frequency, to what should be 368639844 Hz, the
> > actual output frequency of the pll is 737279687 Hz (as reported by the
> > debugfs clk_summary entry), which is double the expect frequency. The
> > calculations for the pll frequency appear to be correct and the problem
> > is caused by incorrect divider settings for the pll_a in the look-up
> > table of multipliers and dividers. The P dividers for all entries in the
> > table are all one less than they should be. Fix this by increasing the
> > value of the P dividers by 1 to get the expected rates.
> > 
> > The rates in the table have been verified using the following equations:
> > 
> > 1. Integer NDIV (SDM_DIN = 0)
> >    fout = (fref * n) / (m * p)
> > 
> > 2. Fractional NDIV
> >    fout = (fref * (n + 0.5 + (SDM_DIN/8192))) / (m * p)
> > 
> > Where SDM_DIN is a signed 16-bit value between 0xf000 and 0x1000.
> > 
> > Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> > ---
> > 
> > Thierry, Rhyland, please note that after this change, the pll_a settings
> > match those in the nvidia downstream 3.18 kernel for Tegra210.
> > 
> >
> 
> This was an issue we had before/around merging T210 driver. The tegra
> clock code was inconsistent in how it treated the pdiv. In some places
> it stored the direct HW value in the frequency table entry struct (like
> in the predefined frequencies like what you changed). Some places stored
> the translated (=_hw_to_p_div()). This is most commonly a difference in
> a factor of 2.
> 
> I found when initially doing the T210 that most clocks I requested rates
> for came out at either 1/2 or 2x what I wanted depending on the path.
> 
> I think when Thierry merged my series, he added some code to address
> this issue, as he saw it too I think. Depending on what his change was
> (to consistently store either pdiv or hw_val) then we may need to adjust
> ALL the predefined rates in the clk-tegra210 code.
> 
> Thierry, do you remember off-hand what you changed for that?

Yes. The problem was that we were inconsistently treating the P-divider
values in frequency tables. In some cases they were assumed to be the
real divider values, whereas in other cases they were treated as being
the direct register values.

This was changed to be consistent in commit 86c679a52294 ("clk: tegra:
pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") but I
must have forgotten to update the Tegra210 frequency tables with a
corresponding change.

I've sent out a patch that should fix those all up since the same error
exists for many others.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]