Re: [PATCH V6 05/10] Documentation: DT: bindings: Add power domain info for NVIDIA PMC

Thierry Reding
2016-02-29T07:22:21Z

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On Fri, Feb 26, 2016 at 03:48:39PM +0000, Jon Hunter wrote:
> Add power-domain binding documentation for the NVIDIA PMC driver in
> order to support generic power-domains.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 61 ++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> index 53aa5496c5cf..0c383a9e720e 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> @@ -1,5 +1,7 @@
> NVIDIA Tegra Power Management Controller (PMC)
>
> +== Power Management Controller Node ==
> +
> The PMC block interacts with an external Power Management Unit. The PMC
> mostly controls the entry and exit of the system from different sleep
> modes. It provides power-gating controllers for SoC and CPU power-islands.
> @@ -70,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
> Defaults to 0. Valid values are described in section 12.5.2
> "Pinmux Support" of the Tegra4 Technical Reference Manual.
>
> +Optional nodes:
> +- powergates : This node contains a hierarchy of power domain nodes, which
> + should match the powergates on the Tegra SoC. See "Powergate
> + Nodes" below.
> +
> Example:
>
> / SoC dts including file
> @@ -115,3 +122,57 @@ pmc@7000f400 {
> };
> ...
> };
> +
> +
> +== Powergate Nodes ==
> +
> +Each of the powergate nodes represents a power-domain on the Tegra SoC
> +that can be power-gated by the PMC and should be named appropriately.
> +
> +Required properties:
> + - reg: Contains an integer value that identifies the PMC power-gate.
> + Please refer to the Tegra TRM for more details. The parent node
> + must contain the following two properties:
> + - #address-cells: Must be 1,
> + - #size-cells: Must be 0.
> + - clocks: Must contain an entry for each clock required by the PMC for
> + controlling a power-gate. See ../clocks/clock-bindings.txt for details.
> + - resets: Must contain an entry for each reset required by the PMC for
> + controlling a power-gate. See ../reset/reset.txt for details.
> + - #power-domain-cells: Must be 0.
> +
> +Example:
> +
> + pmc: pmc@0,7000e400 {
> + compatible = "nvidia,tegra210-pmc";
> + reg = <0x0 0x7000e400 0x0 0x400>;
> + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
> + clock-names = "pclk", "clk32k_in";
> +
> + powergates {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_audio: aud {
> + reg = <TEGRA_POWERGATE_AUD>;
> + clocks = <&tegra_car TEGRA210_CLK_APE>,
> + <&tegra_car TEGRA210_CLK_APB2APE>;
> + resets = <&tegra_car 198>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };

Should we not spell out the list of supported power domains per SoC
here? The example gives only one, but we have a bunch of others. If they
can be referred to by phandle I'd expect there to be a list of them. I'm
not sure if this was discussed earlier, but does it perhaps make sense
to tie names to IDs, such that we don't need the reg property? That'd be
analogous to how PMICs define regulators.

The reason why I'm asking is that in the above example it's possible to
have this:

pd_audio: pcie {
reg = <TEGRA_POWERGATE_SOR>;
...
};

And there'd be no way to sanity check other than by human inspection.
Perhaps I'm being overly paranoid and we can easily filter these out
during code review.

I suppose that if Rob's fine with it, I can be too.

Thierry

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