From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Date: Thu, 17 Mar 2016 11:26:31 -0500 Message-ID: <20160317162631.GA6858@rob-hp-laptop> References: <1457452094-5409-1-git-send-email-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1457452094-5409-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Bjorn Helgaas , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Alexandre Courbot , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On Tue, Mar 08, 2016 at 04:48:13PM +0100, Thierry Reding wrote: > From: Thierry Reding > > Changes to the pad controller device tree binding have required that > each lane be associated with a separate PHY. Update the PCI host bridge > device tree binding to allow each root port to define the list of PHYs > required to drive the lanes associated with it. > > Signed-off-by: Thierry Reding > --- > .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) Acked-by: Rob Herring