From: Thierry Reding <thierry.reding@gmail.com>
To: Penny Chiu <pchiu@nvidia.com>
Cc: swarren@wwwdotorg.org, gnurou@gmail.com, pdeschrijver@nvidia.com,
pgaikwad@nvidia.com, rjw@rjwysocki.net, viresh.kumar@linaro.org,
mturquette@baylibre.com, sboyd@codeaurora.org,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-pwm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id
Date: Fri, 22 Apr 2016 15:04:09 +0200 [thread overview]
Message-ID: <20160422130409.GK9047@ulmo.ba.sec> (raw)
In-Reply-To: <1461321071-6431-3-git-send-email-pchiu@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 4003 bytes --]
On Fri, Apr 22, 2016 at 06:31:02PM +0800, Penny Chiu wrote:
> Move all SoC specific fcpu data into of_device_id structure, and
> move SoC fcpu data assignments from init function to probe
> function.
>
> Signed-off-by: Penny Chiu <pchiu@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 51 ++++++++++++++++++++++--------
> 1 file changed, 37 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index 5e5958e..b577bc6 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -21,6 +21,7 @@
> #include <linux/err.h>
> #include <linux/kernel.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <soc/tegra/fuse.h>
>
> @@ -28,8 +29,15 @@
> #include "clk-dfll.h"
> #include "cvb.h"
>
> +struct dfll_fcpu_data {
> + const unsigned long *cpu_max_freq_table;
> + unsigned int cpu_max_freq_table_size;
> + const struct cvb_table *cpu_cvb_tables;
> + unsigned int cpu_cvb_tables_size;
> +};
> +
> /* Maximum CPU frequency, indexed by CPU speedo id */
> -static const unsigned long cpu_max_freq_table[] = {
> +static const unsigned long tegra124_cpu_max_freq_table[] = {
> [0] = 2014500000UL,
> [1] = 2320500000UL,
> [2] = 2116500000UL,
> @@ -79,18 +87,39 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
> },
> };
>
> +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
> + .cpu_max_freq_table = tegra124_cpu_max_freq_table,
> + .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
> + .cpu_cvb_tables = tegra124_cpu_cvb_tables,
> + .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
> +};
> +
> +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
There's no need to prefix this with tegra124_ since obviously the goal
is to make this a table that works at least on Tegra210 as well.
> + {
> + .compatible = "nvidia,tegra124-dfll",
> + .data = &tegra124_dfll_fcpu_data
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, tegra124_dfll_fcpu_of_match);
> +
> static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
> {
> int process_id, speedo_id, speedo_value, ret;
> struct rail_alignment align;
> struct tegra_dfll_soc_data *soc;
> const struct cvb_table *cvb;
> + const struct of_device_id *of_id;
> + const struct dfll_fcpu_data *fcpu_data;
> +
> + of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev);
> + fcpu_data = of_id->data;
You should be using of_device_get_match_data() nowadays. That allows you
to do this in one step while at the same time allowing to keep the match
tables where they are.
>
> process_id = tegra_sku_info.cpu_process_id;
> speedo_id = tegra_sku_info.cpu_speedo_id;
> speedo_value = tegra_sku_info.cpu_speedo_value;
>
> - if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
> + if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
> dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
> speedo_id);
> return -ENODEV;
> @@ -121,12 +150,12 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - cvb = tegra_cvb_build_opp_table(tegra124_cpu_cvb_tables,
> - ARRAY_SIZE(tegra124_cpu_cvb_tables),
> - &align,
> - process_id, speedo_id, speedo_value,
> - cpu_max_freq_table[speedo_id],
> - soc->dev);
> + cvb = tegra_cvb_build_opp_table(fcpu_data->cpu_cvb_tables,
> + fcpu_data->cpu_cvb_tables_size,
> + &align,
> + process_id, speedo_id, speedo_value,
> + fcpu_data->cpu_max_freq_table[speedo_id],
> + soc->dev);
This, and potentially other parts will conflict with some cleanup I
recently did to this code. You may want to rebase on some linux-next
earlier next week which should have those cleanup patches.
Thierry
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next prev parent reply other threads:[~2016-04-22 13:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-22 10:31 [PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu
2016-04-22 10:31 ` [PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu
2016-04-22 10:31 ` [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu
2016-04-22 13:04 ` Thierry Reding [this message]
2016-04-22 10:31 ` [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu
2016-04-22 13:11 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu
2016-04-22 13:16 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu
2016-04-22 12:55 ` Thierry Reding
2016-05-06 23:15 ` Stephen Boyd
2016-05-06 23:21 ` Stephen Warren
2016-04-22 10:31 ` [PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu
2016-04-22 10:31 ` [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu
[not found] ` <1461321071-6431-8-git-send-email-pchiu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-04-22 11:00 ` Viresh Kumar
2016-04-22 10:31 ` [PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu
2016-04-22 10:31 ` [PATCH 09/11] arm64: tegra: Add DFLL clock node " Penny Chiu
[not found] ` <1461321071-6431-10-git-send-email-pchiu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-04-22 13:28 ` Thierry Reding
2016-04-22 10:31 ` [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu
2016-04-22 11:44 ` Jon Hunter
2016-04-22 13:23 ` Thierry Reding
2016-04-22 13:36 ` Jon Hunter
[not found] ` <1461321071-6431-1-git-send-email-pchiu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-04-22 10:31 ` [PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu
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