From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 Date: Wed, 24 Aug 2016 10:54:19 -0700 Message-ID: <20160824175419.GD19826@codeaurora.org> References: <20160824135656.5025-1-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20160824135656.5025-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Michael Turquette , Jonathan Hunter , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 08/24, Thierry Reding wrote: > From: Vince Hsu > > Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when > the DIS power domain is during up-powergating process but the clamp to this > domain is not removed yet. That causes a timeout and aborts the power > sequence, although the PLLD/PLLD2 has already locked. To remove the false > alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the > clocks as locked. > > Signed-off-by: Vince Hsu > Tested-by: Jonathan Hunter > Signed-off-by: Thierry Reding > --- Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project