[PATCH 01/11] arm64: tegra: Add PMC controller on Tegra186

[PATCH 01/11] arm64: tegra: Add PMC controller on Tegra186

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 62fa85ae0271..d6955bb46ae0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -307,6 +307,15 @@
 		#interrupt-cells = <2>;
 	};
 
+	pmc@c360000 {
+		compatible = "nvidia,tegra186-pmc";
+		reg = <0 0x0c360000 0 0x10000>,
+		      <0 0x0c370000 0 0x10000>,
+		      <0 0x0c380000 0 0x10000>,
+		      <0 0x0c390000 0 0x10000>;
+		reg-names = "pmc", "wake", "aotag", "scratch";
+	};
+
 	sysram@30000000 {
 		compatible = "nvidia,tegra186-sysram", "mmio-sram";
 		reg = <0x0 0x30000000 0x0 0x50000>;
-- 
2.11.1

[PATCH 02/11] arm64: tegra: Add ethernet support for Tegra186

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data
transfer rates.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index d6955bb46ae0..3ea5e6369bc3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -27,6 +27,37 @@
 		gpio-controller;
 	};
 
+	ethernet@2490000 {
+		compatible = "nvidia,tegra186-eqos",
+			     "snps,dwc-qos-ethernet-4.10";
+		reg = <0x0 0x02490000 0x0 0x10000>;
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
+			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
+			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
+			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
+			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
+			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
+			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
+			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
+			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
+			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
+		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
+			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
+			 <&bpmp TEGRA186_CLK_EQOS_RX>,
+			 <&bpmp TEGRA186_CLK_EQOS_TX>,
+			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
+		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
+		resets = <&bpmp TEGRA186_RESET_EQOS>;
+		reset-names = "eqos";
+		status = "disabled";
+
+		snps,write-requests = <1>;
+		snps,read-requests = <3>;
+		snps,burst-map = <0x7>;
+		snps,txpbl = <32>;
+		snps,rxpbl = <8>;
+	};
+
 	uarta: serial@3100000 {
 		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 		reg = <0x0 0x03100000 0x0 0x40>;
-- 
2.11.1

[PATCH 03/11] arm64: tegra: Invert the PMC interrupt on P3310

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The PMC interrupt is inverted on P3310, so mark it as such in the device
tree to avoid a flood of interrupts when the PMIC is enabled.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 1abe2eceb3d1..3653d0dd5f4f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -26,6 +26,10 @@
 		status = "okay";
 	};
 
+	pmc@c360000 {
+		nvidia,invert-interrupt;
+	};
+
 	cpus {
 		cpu@0 {
 			enable-method = "psci";
-- 
2.11.1

[PATCH 04/11] arm64: tegra: Enable I2C controllers on P3310

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P3310 processor modules use seven I2C controllers for various
peripherals.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 40 +++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 3653d0dd5f4f..762f4756346c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -6,6 +6,14 @@
 
 	aliases {
 		serial0 = &uarta;
+		i2c0 = "/bpmp/i2c";
+		i2c1 = "/i2c@3160000";
+		i2c2 = "/i2c@c240000";
+		i2c3 = "/i2c@3180000";
+		i2c4 = "/i2c@3190000";
+		i2c5 = "/i2c@31c0000";
+		i2c6 = "/i2c@c250000";
+		i2c7 = "/i2c@31e0000";
 	};
 
 	chosen {
@@ -22,10 +30,38 @@
 		status = "okay";
 	};
 
+	i2c@3160000 {
+		status = "okay";
+	};
+
+	i2c@3180000 {
+		status = "okay";
+	};
+
+	i2c@3190000 {
+		status = "okay";
+	};
+
+	i2c@31c0000 {
+		status = "okay";
+	};
+
+	i2c@31e0000 {
+		status = "okay";
+	};
+
 	hsp@3c00000 {
 		status = "okay";
 	};
 
+	i2c@c240000 {
+		status = "okay";
+	};
+
+	i2c@c250000 {
+		status = "okay";
+	};
+
 	pmc@c360000 {
 		nvidia,invert-interrupt;
 	};
@@ -57,7 +93,9 @@
 	};
 
 	bpmp {
-		status = "okay";
+		i2c {
+			status = "okay";
+		};
 	};
 
 	psci {
-- 
2.11.1

[PATCH 05/11] arm64: tegra: Enable ethernet on P3310

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P3310 processor module provides networking via the ethernet
controller found on NVIDIA Tegra186 SoCs.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 762f4756346c..ffbb4be5122e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -26,6 +26,26 @@
 		reg = <0x0 0x80000000 0x2 0x00000000>;
 	};
 
+	ethernet@2490000 {
+		status = "okay";
+
+		phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+		phy-handle = <&phy>;
+		phy-mode = "rgmii";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy: phy@0 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0x0>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+
 	serial@3100000 {
 		status = "okay";
 	};
-- 
2.11.1

[PATCH 06/11] arm64: tegra: Add initial power tree for P3310

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed
regulators to model the power tree.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 211 +++++++++++++++++++++++++
 1 file changed, 211 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index ffbb4be5122e..1a9ac73b4ecb 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -1,5 +1,7 @@
 #include "tegra186.dtsi"
 
+#include <dt-bindings/mfd/max77620.h>
+
 / {
 	model = "NVIDIA Tegra186 P3310 Processor Module";
 	compatible = "nvidia,p3310", "nvidia,tegra186";
@@ -115,6 +117,180 @@
 	bpmp {
 		i2c {
 			status = "okay";
+
+			pmic: pmic@3c {
+				compatible = "maxim,max77620";
+				reg = <0x3c>;
+
+				interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+
+				#gpio-cells = <2>;
+				gpio-controller;
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&max77620_default>;
+
+				max77620_default: pinmux {
+					gpio0 {
+						pins = "gpio0";
+						function = "gpio";
+					};
+
+					gpio1 {
+						pins = "gpio1";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+					};
+
+					gpio2 {
+						pins = "gpio2";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+					};
+
+					gpio3 {
+						pins = "gpio3";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+					};
+
+					gpio4 {
+						pins = "gpio4";
+						function = "32k-out1";
+						drive-push-pull = <1>;
+					};
+
+					gpio5 {
+						pins = "gpio5";
+						function = "gpio";
+						drive-push-pull = <0>;
+					};
+
+					gpio6 {
+						pins = "gpio6";
+						function = "gpio";
+						drive-push-pull = <1>;
+					};
+
+					gpio7 {
+						pins = "gpio7";
+						function = "gpio";
+						drive-push-pull = <0>;
+					};
+				};
+
+				fps {
+					fps0 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+
+					fps1 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+
+					fps2 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+				};
+
+				regulators {
+					in-sd0-supply = <&vdd_5v0_sys>;
+					in-sd1-supply = <&vdd_5v0_sys>;
+					in-sd2-supply = <&vdd_5v0_sys>;
+					in-sd3-supply = <&vdd_5v0_sys>;
+
+					in-ldo0-1-supply = <&vdd_5v0_sys>;
+					in-ldo2-supply = <&vdd_5v0_sys>;
+					in-ldo3-5-supply = <&vdd_5v0_sys>;
+					in-ldo4-6-supply = <&vdd_1v8>;
+					in-ldo7-8-supply = <&avdd_dsi_csi>;
+
+					sd0 {
+						regulator-name = "VDD_DDR_1V1_PMIC";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <1100000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					avdd_dsi_csi: sd1 {
+						regulator-name = "AVDD_DSI_CSI_1V2";
+						regulator-min-microvolt = <1200000>;
+						regulator-max-microvolt = <1200000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_1v8: sd2 {
+						regulator-name = "VDD_1V8";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_3v3_sys: sd3 {
+						regulator-name = "VDD_3V3_SYS";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					ldo0 {
+						regulator-name = "VDD_1V8_AP_PLL";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					ldo2 {
+						regulator-name = "VDDIO_3V3_AOHV";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vddio_sdmmc1: ldo3 {
+						regulator-name = "VDDIO_SDMMC1_AP";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <3300000>;
+					};
+
+					ldo4 {
+						regulator-name = "VDD_RTC";
+						regulator-min-microvolt = <1000000>;
+						regulator-max-microvolt = <1000000>;
+					};
+
+					vddio_sdmmc3: ldo5 {
+						regulator-name = "VDDIO_SDMMC3_AP";
+						regulator-min-microvolt = <2800000>;
+						regulator-max-microvolt = <2800000>;
+					};
+
+					vdd_pex: ldo7 {
+						regulator-name = "VDD_PEX_1V05";
+						regulator-min-microvolt = <1050000>;
+						regulator-max-microvolt = <1050000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+				};
+			};
 		};
 	};
 
@@ -123,4 +299,39 @@
 		status = "okay";
 		method = "smc";
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_sys: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+
+			regulator-name = "VDD_5V0_SYS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_1v8_ap: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+
+			regulator-name = "VDD_1V8_AP";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+
+			/* XXX */
+			regulator-always-on;
+			regulator-boot-on;
+
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+
+			vin-supply = <&vdd_1v8>;
+		};
+	};
 };
-- 
2.11.1

[PATCH 07/11] arm64: tegra: Enable SDHCI controllers on P3110

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P3110 processor module wires one of the SDHCI controllers to an on-
board eMMC and exposes another set of SD/MMC signals on the connector to
support an external SD/MMC card. A third controller is connected to the
SDIO pins of an M.2 KEY E connector.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 42 ++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 1a9ac73b4ecb..b18e166527d8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -7,6 +7,8 @@
 	compatible = "nvidia,p3310", "nvidia,tegra186";
 
 	aliases {
+		sdhci0 = "/sdhci@3460000";
+		sdhci1 = "/sdhci@3400000";
 		serial0 = &uarta;
 		i2c0 = "/bpmp/i2c";
 		i2c1 = "/i2c@3160000";
@@ -72,6 +74,32 @@
 		status = "okay";
 	};
 
+	/* SDMMC1 (SD/MMC) */
+	sdhci@3400000 {
+		status = "okay";
+
+		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
+
+		vqmmc-supply = <&vddio_sdmmc1>;
+		vmmc-supply = <&vdd_sd>;
+	};
+
+	/* SDMMC3 (SDIO) */
+	sdhci@3440000 {
+		status = "okay";
+	};
+
+	/* SDMMC4 (eMMC) */
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vqmmc-supply = <&vdd_1v8_ap>;
+		vmmc-supply = <&vdd_3v3_sys>;
+	};
+
 	hsp@3c00000 {
 		status = "okay";
 	};
@@ -333,5 +361,19 @@
 
 			vin-supply = <&vdd_1v8>;
 		};
+
+		vdd_sd: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+
+			regulator-name = "SD_CARD_SW_PWR";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+
+			gpio = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+
+			vin-supply = <&vdd_3v3_sys>;
+		};
 	};
 };
-- 
2.11.1

[PATCH 08/11] arm64: tegra: Enable current monitors on P3310

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P3310 processor module contains two current monitors that can be
used to determine the current flow across various parts of the board
design.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index b18e166527d8..a1cb6b35314e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,16 @@
 
 	i2c@3160000 {
 		status = "okay";
+
+		power-monitor@40 {
+			compatible = "ti,ina3221";
+			reg = <0x40>;
+		};
+
+		power-monitor@41 {
+			compatible = "ti,ina3221";
+			reg = <0x41>;
+		};
 	};
 
 	i2c@3180000 {
-- 
2.11.1

[PATCH 09/11] arm64: tegra: Add GPIO keys on P2771

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P2771 has three keys (power, volume up and volume down) that are
connected to pins on the AON GPIO controller.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 0d3c0996d832..1c195d71806d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -1,8 +1,42 @@
 /dts-v1/;
 
+#include <dt-bindings/input/linux-event-codes.h>
+
 #include "tegra186-p3310.dtsi"
 
 / {
 	model = "NVIDIA Tegra186 P2771-0000 Development Board";
 	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
+					   GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_POWER>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
+					   GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <10>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
+					   GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			debounce-interval = <10>;
+		};
+	};
 };
-- 
2.11.1

[PATCH 10/11] arm64: tegra: Add power monitors on P2771

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P2771 development board comes with two power monitors that can be
used to determine power consumption in different parts of the board.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 1c195d71806d..9485841e3351 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -8,6 +8,18 @@
 	model = "NVIDIA Tegra186 P2771-0000 Development Board";
 	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
 
+	i2c@3160000 {
+		power-monitor@42 {
+			compatible = "ti,ina3221";
+			reg = <0x42>;
+		};
+
+		power-monitor@43 {
+			compatible = "ti,ina3221";
+			reg = <0x43>;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
-- 
2.11.1

[PATCH 11/11] arm64: tegra: Add GPIO expanders on P2771

[Thierry Reding]

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The P2771 development board expands the number of GPIOs via two I2C
chips.

Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 9485841e3351..eac75764bf3c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -18,6 +18,28 @@
 			compatible = "ti,ina3221";
 			reg = <0x43>;
 		};
+
+		exp1: gpio@74 {
+			compatible = "ti,tca9539";
+			reg = <0x74>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+		};
+
+		exp2: gpio@77 {
+			compatible = "ti,tca9539";
+			reg = <0x77>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+		};
 	};
 
 	gpio-keys {
-- 
2.11.1

Re: [PATCH 01/11] arm64: tegra: Add PMC controller on Tegra186

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 62fa85ae0271..d6955bb46ae0 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -307,6 +307,15 @@
>  		#interrupt-cells = <2>;
>  	};
>  
> +	pmc@c360000 {
> +		compatible = "nvidia,tegra186-pmc";
> +		reg = <0 0x0c360000 0 0x10000>,
> +		      <0 0x0c370000 0 0x10000>,
> +		      <0 0x0c380000 0 0x10000>,
> +		      <0 0x0c390000 0 0x10000>;
> +		reg-names = "pmc", "wake", "aotag", "scratch";
> +	};
> +
>  	sysram@30000000 {
>  		compatible = "nvidia,tegra186-sysram", "mmio-sram";
>  		reg = <0x0 0x30000000 0x0 0x50000>;
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 03/11] arm64: tegra: Invert the PMC interrupt on P3310

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The PMC interrupt is inverted on P3310, so mark it as such in the device
> tree to avoid a flood of interrupts when the PMIC is enabled.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 1abe2eceb3d1..3653d0dd5f4f 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -26,6 +26,10 @@
>  		status = "okay";
>  	};
>  
> +	pmc@c360000 {
> +		nvidia,invert-interrupt;
> +	};
> +

It is probably over-kill to register the pmc as an irq-controller just
to set the 'type' and then hook up the pmic interrupt to the pmc and not
directly gic. So ...

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 04/11] arm64: tegra: Enable I2C controllers on P3310

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P3310 processor modules use seven I2C controllers for various
> peripherals.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 40 +++++++++++++++++++++++++-
>  1 file changed, 39 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 3653d0dd5f4f..762f4756346c 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -6,6 +6,14 @@
>  
>  	aliases {
>  		serial0 = &uarta;
> +		i2c0 = "/bpmp/i2c";
> +		i2c1 = "/i2c@3160000";
> +		i2c2 = "/i2c@c240000";
> +		i2c3 = "/i2c@3180000";
> +		i2c4 = "/i2c@3190000";
> +		i2c5 = "/i2c@31c0000";
> +		i2c6 = "/i2c@c250000";
> +		i2c7 = "/i2c@31e0000";

Does it matter that these aliases do not align with the TRM numbering? I
know that if we did it would create holes but I was not sure if that
would be clearer?

>  	};
>  
>  	chosen {
> @@ -22,10 +30,38 @@
>  		status = "okay";
>  	};
>  
> +	i2c@3160000 {
> +		status = "okay";
> +	};
> +
> +	i2c@3180000 {
> +		status = "okay";
> +	};
> +
> +	i2c@3190000 {
> +		status = "okay";
> +	};
> +
> +	i2c@31c0000 {
> +		status = "okay";
> +	};
> +
> +	i2c@31e0000 {
> +		status = "okay";
> +	};
> +
>  	hsp@3c00000 {
>  		status = "okay";
>  	};
>  
> +	i2c@c240000 {
> +		status = "okay";
> +	};
> +
> +	i2c@c250000 {
> +		status = "okay";
> +	};
> +
>  	pmc@c360000 {
>  		nvidia,invert-interrupt;
>  	};
> @@ -57,7 +93,9 @@
>  	};
>  
>  	bpmp {
> -		status = "okay";
> +		i2c {
> +			status = "okay";
> +		};
>  	};
>  
>  	psci {
> 

Otherwise ...

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 02/11] arm64: tegra: Add ethernet support for Tegra186

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
> ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data
> transfer rates.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index d6955bb46ae0..3ea5e6369bc3 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -27,6 +27,37 @@
>  		gpio-controller;
>  	};
>  
> +	ethernet@2490000 {
> +		compatible = "nvidia,tegra186-eqos",
> +			     "snps,dwc-qos-ethernet-4.10";
> +		reg = <0x0 0x02490000 0x0 0x10000>;
> +		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
> +			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
> +			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
> +			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
> +			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
> +			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
> +			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
> +			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
> +			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
> +			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
> +		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
> +			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
> +			 <&bpmp TEGRA186_CLK_EQOS_RX>,
> +			 <&bpmp TEGRA186_CLK_EQOS_TX>,
> +			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
> +		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
> +		resets = <&bpmp TEGRA186_RESET_EQOS>;
> +		reset-names = "eqos";
> +		status = "disabled";
> +
> +		snps,write-requests = <1>;
> +		snps,read-requests = <3>;
> +		snps,burst-map = <0x7>;
> +		snps,txpbl = <32>;
> +		snps,rxpbl = <8>;
> +	};
> +
>  	uarta: serial@3100000 {
>  		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
>  		reg = <0x0 0x03100000 0x0 0x40>;
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 05/11] arm64: tegra: Enable ethernet on P3310

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P3310 processor module provides networking via the ethernet
> controller found on NVIDIA Tegra186 SoCs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 762f4756346c..ffbb4be5122e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -26,6 +26,26 @@
>  		reg = <0x0 0x80000000 0x2 0x00000000>;
>  	};
>  
> +	ethernet@2490000 {
> +		status = "okay";
> +
> +		phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
> +		phy-handle = <&phy>;
> +		phy-mode = "rgmii";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			phy: phy@0 {
> +				compatible = "ethernet-phy-ieee802.3-c22";
> +				reg = <0x0>;
> +				interrupt-parent = <&gpio>;
> +				interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +	};
> +
>  	serial@3100000 {
>  		status = "okay";
>  	};

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 06/11] arm64: tegra: Add initial power tree for P3310

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed
> regulators to model the power tree.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 211 +++++++++++++++++++++++++
>  1 file changed, 211 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index ffbb4be5122e..1a9ac73b4ecb 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -1,5 +1,7 @@
>  #include "tegra186.dtsi"
>  
> +#include <dt-bindings/mfd/max77620.h>
> +
>  / {
>  	model = "NVIDIA Tegra186 P3310 Processor Module";
>  	compatible = "nvidia,p3310", "nvidia,tegra186";
> @@ -115,6 +117,180 @@
>  	bpmp {
>  		i2c {
>  			status = "okay";
> +
> +			pmic: pmic@3c {
> +				compatible = "maxim,max77620";
> +				reg = <0x3c>;
> +
> +				interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&max77620_default>;
> +
> +				max77620_default: pinmux {
> +					gpio0 {
> +						pins = "gpio0";
> +						function = "gpio";
> +					};
> +
> +					gpio1 {
> +						pins = "gpio1";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
> +					};
> +
> +					gpio2 {
> +						pins = "gpio2";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
> +					};
> +
> +					gpio3 {
> +						pins = "gpio3";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
> +					};
> +
> +					gpio4 {
> +						pins = "gpio4";
> +						function = "32k-out1";
> +						drive-push-pull = <1>;
> +					};
> +
> +					gpio5 {
> +						pins = "gpio5";
> +						function = "gpio";
> +						drive-push-pull = <0>;
> +					};
> +
> +					gpio6 {
> +						pins = "gpio6";
> +						function = "gpio";
> +						drive-push-pull = <1>;
> +					};
> +
> +					gpio7 {
> +						pins = "gpio7";
> +						function = "gpio";
> +						drive-push-pull = <0>;
> +					};
> +				};
> +
> +				fps {
> +					fps0 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +
> +					fps1 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +
> +					fps2 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +				};
> +
> +				regulators {
> +					in-sd0-supply = <&vdd_5v0_sys>;
> +					in-sd1-supply = <&vdd_5v0_sys>;
> +					in-sd2-supply = <&vdd_5v0_sys>;
> +					in-sd3-supply = <&vdd_5v0_sys>;
> +
> +					in-ldo0-1-supply = <&vdd_5v0_sys>;
> +					in-ldo2-supply = <&vdd_5v0_sys>;
> +					in-ldo3-5-supply = <&vdd_5v0_sys>;
> +					in-ldo4-6-supply = <&vdd_1v8>;
> +					in-ldo7-8-supply = <&avdd_dsi_csi>;
> +
> +					sd0 {
> +						regulator-name = "VDD_DDR_1V1_PMIC";
> +						regulator-min-microvolt = <1100000>;
> +						regulator-max-microvolt = <1100000>;
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					avdd_dsi_csi: sd1 {
> +						regulator-name = "AVDD_DSI_CSI_1V2";
> +						regulator-min-microvolt = <1200000>;
> +						regulator-max-microvolt = <1200000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vdd_1v8: sd2 {
> +						regulator-name = "VDD_1V8";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <1800000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vdd_3v3_sys: sd3 {
> +						regulator-name = "VDD_3V3_SYS";
> +						regulator-min-microvolt = <3300000>;
> +						regulator-max-microvolt = <3300000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					ldo0 {
> +						regulator-name = "VDD_1V8_AP_PLL";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <1800000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					ldo2 {
> +						regulator-name = "VDDIO_3V3_AOHV";
> +						regulator-min-microvolt = <3300000>;
> +						regulator-max-microvolt = <3300000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vddio_sdmmc1: ldo3 {
> +						regulator-name = "VDDIO_SDMMC1_AP";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <3300000>;
> +					};
> +
> +					ldo4 {
> +						regulator-name = "VDD_RTC";
> +						regulator-min-microvolt = <1000000>;
> +						regulator-max-microvolt = <1000000>;
> +					};
> +
> +					vddio_sdmmc3: ldo5 {
> +						regulator-name = "VDDIO_SDMMC3_AP";
> +						regulator-min-microvolt = <2800000>;
> +						regulator-max-microvolt = <2800000>;
> +					};
> +
> +					vdd_pex: ldo7 {
> +						regulator-name = "VDD_PEX_1V05";
> +						regulator-min-microvolt = <1050000>;
> +						regulator-max-microvolt = <1050000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};

On the schematics for I am looking at (for the c03 version) I see:

ldo7 --> VDD_HDMI_1V05
ldo8 --> VDD_PEX_1V05

> +				};
> +			};
>  		};
>  	};
>  
> @@ -123,4 +299,39 @@
>  		status = "okay";
>  		method = "smc";
>  	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_5v0_sys: regulator@0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +
> +			regulator-name = "VDD_5V0_SYS";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +		};
> +
> +		vdd_1v8_ap: regulator@1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +
> +			regulator-name = "VDD_1V8_AP";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +
> +			/* XXX */
> +			regulator-always-on;
> +			regulator-boot-on;
> +
> +			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +
> +			vin-supply = <&vdd_1v8>;
> +		};
> +	};
>  };
> 

Otherwise looks good.

Cheers
Jon

-- 
nvpublic

Re: [PATCH 07/11] arm64: tegra: Enable SDHCI controllers on P3110

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P3110 processor module wires one of the SDHCI controllers to an on-
> board eMMC and exposes another set of SD/MMC signals on the connector to
> support an external SD/MMC card. A third controller is connected to the
> SDIO pins of an M.2 KEY E connector.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 42 ++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 1a9ac73b4ecb..b18e166527d8 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -7,6 +7,8 @@
>  	compatible = "nvidia,p3310", "nvidia,tegra186";
>  
>  	aliases {
> +		sdhci0 = "/sdhci@3460000";
> +		sdhci1 = "/sdhci@3400000";

Any reason why you don't include all 3 sdhci controllers here?

>  		serial0 = &uarta;
>  		i2c0 = "/bpmp/i2c";
>  		i2c1 = "/i2c@3160000";
> @@ -72,6 +74,32 @@
>  		status = "okay";
>  	};
>  
> +	/* SDMMC1 (SD/MMC) */
> +	sdhci@3400000 {
> +		status = "okay";
> +
> +		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>;

I see the CD as P-5 and not P-6 on the schematic.

> +		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
> +
> +		vqmmc-supply = <&vddio_sdmmc1>;
> +		vmmc-supply = <&vdd_sd>;

The card slot is on the carrier board and although the cd and wp pins
are allocated on the cvm, I did not see a reference to the vmmc-supply
on the cvm. So should the 'vmmc-supply' be in the carrier board file?

> +	};
> +
> +	/* SDMMC3 (SDIO) */
> +	sdhci@3440000 {
> +		status = "okay";
> +	};
> +
> +	/* SDMMC4 (eMMC) */
> +	sdhci@3460000 {
> +		status = "okay";
> +		bus-width = <8>;
> +		non-removable;
> +
> +		vqmmc-supply = <&vdd_1v8_ap>;
> +		vmmc-supply = <&vdd_3v3_sys>;
> +	};
> +
>  	hsp@3c00000 {
>  		status = "okay";
>  	};
> @@ -333,5 +361,19 @@
>  
>  			vin-supply = <&vdd_1v8>;
>  		};
> +
> +		vdd_sd: regulator@2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +
> +			regulator-name = "SD_CARD_SW_PWR";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +
> +			gpio = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;

Here I see the gpio as P-6 and not P-5.
	
> +			enable-active-high;
> +
> +			vin-supply = <&vdd_3v3_sys>;
> +		};
>  	};
>  };

I also see the above regulator on the carrier board and not on the cvm.

Cheers
Jon

-- 
nvpublic

Re: [PATCH 08/11] arm64: tegra: Enable current monitors on P3310

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P3310 processor module contains two current monitors that can be
> used to determine the current flow across various parts of the board
> design.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index b18e166527d8..a1cb6b35314e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -56,6 +56,16 @@
>  
>  	i2c@3160000 {
>  		status = "okay";
> +
> +		power-monitor@40 {
> +			compatible = "ti,ina3221";
> +			reg = <0x40>;
> +		};
> +
> +		power-monitor@41 {
> +			compatible = "ti,ina3221";
> +			reg = <0x41>;
> +		};
>  	};
>  
>  	i2c@3180000 {
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 09/11] arm64: tegra: Add GPIO keys on P2771

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P2771 has three keys (power, volume up and volume down) that are
> connected to pins on the AON GPIO controller.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 34 ++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 0d3c0996d832..1c195d71806d 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -1,8 +1,42 @@
>  /dts-v1/;
>  
> +#include <dt-bindings/input/linux-event-codes.h>
> +
>  #include "tegra186-p3310.dtsi"
>  
>  / {
>  	model = "NVIDIA Tegra186 P2771-0000 Development Board";
>  	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		power {
> +			label = "Power";
> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
> +					   GPIO_ACTIVE_LOW>;
> +			linux,input-type = <EV_KEY>;
> +			linux,code = <KEY_POWER>;
> +			debounce-interval = <10>;
> +			wakeup-source;
> +		};
> +
> +		volume-up {
> +			label = "Volume Up";
> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
> +					   GPIO_ACTIVE_LOW>;
> +			linux,input-type = <EV_KEY>;
> +			linux,code = <KEY_VOLUMEUP>;
> +			debounce-interval = <10>;
> +		};

My schematic shows this pin as 'force-recovery'.

> +
> +		volume-down {
> +			label = "Volume Down";
> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
> +					   GPIO_ACTIVE_LOW>;
> +			linux,input-type = <EV_KEY>;
> +			linux,code = <KEY_VOLUMEDOWN>;
> +			debounce-interval = <10>;
> +		};
> +	};
>  };

And this one as 'sleep_l'.

Are these being re-used after boot? I did not find any documentation
about them being used as volume keys.

Cheers
Jon

-- 
nvpublic

Re: [PATCH 10/11] arm64: tegra: Add power monitors on P2771

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P2771 development board comes with two power monitors that can be
> used to determine power consumption in different parts of the board.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 1c195d71806d..9485841e3351 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -8,6 +8,18 @@
>  	model = "NVIDIA Tegra186 P2771-0000 Development Board";
>  	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
>  
> +	i2c@3160000 {
> +		power-monitor@42 {
> +			compatible = "ti,ina3221";
> +			reg = <0x42>;
> +		};
> +
> +		power-monitor@43 {
> +			compatible = "ti,ina3221";
> +			reg = <0x43>;
> +		};
> +	};
> +
>  	gpio-keys {
>  		compatible = "gpio-keys";
>  

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 11/11] arm64: tegra: Add GPIO expanders on P2771

[Jon Hunter]

On 23/02/17 17:30, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P2771 development board expands the number of GPIOs via two I2C
> chips.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 9485841e3351..eac75764bf3c 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -18,6 +18,28 @@
>  			compatible = "ti,ina3221";
>  			reg = <0x43>;
>  		};
> +
> +		exp1: gpio@74 {
> +			compatible = "ti,tca9539";
> +			reg = <0x74>;
> +
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
> +
> +			#gpio-cells = <2>;
> +			gpio-controller;
> +		};
> +
> +		exp2: gpio@77 {
> +			compatible = "ti,tca9539";
> +			reg = <0x77>;
> +
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
> +
> +			#gpio-cells = <2>;
> +			gpio-controller;
> +		};
>  	};
>  
>  	gpio-keys {
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 09/11] arm64: tegra: Add GPIO keys on P2771

[Jon Hunter]

On 08/03/17 12:03, Jon Hunter wrote:
> 
> 
> On 23/02/17 17:30, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The P2771 has three keys (power, volume up and volume down) that are
>> connected to pins on the AON GPIO controller.
>>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 34 ++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
>> index 0d3c0996d832..1c195d71806d 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
>> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
>> @@ -1,8 +1,42 @@
>>  /dts-v1/;
>>  
>> +#include <dt-bindings/input/linux-event-codes.h>
>> +
>>  #include "tegra186-p3310.dtsi"
>>  
>>  / {
>>  	model = "NVIDIA Tegra186 P2771-0000 Development Board";
>>  	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +
>> +		power {
>> +			label = "Power";
>> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
>> +					   GPIO_ACTIVE_LOW>;
>> +			linux,input-type = <EV_KEY>;
>> +			linux,code = <KEY_POWER>;
>> +			debounce-interval = <10>;
>> +			wakeup-source;
>> +		};
>> +
>> +		volume-up {
>> +			label = "Volume Up";
>> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
>> +					   GPIO_ACTIVE_LOW>;
>> +			linux,input-type = <EV_KEY>;
>> +			linux,code = <KEY_VOLUMEUP>;
>> +			debounce-interval = <10>;
>> +		};
> 
> My schematic shows this pin as 'force-recovery'.
> 
>> +
>> +		volume-down {
>> +			label = "Volume Down";
>> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
>> +					   GPIO_ACTIVE_LOW>;
>> +			linux,input-type = <EV_KEY>;
>> +			linux,code = <KEY_VOLUMEDOWN>;
>> +			debounce-interval = <10>;
>> +		};
>> +	};
>>  };
> 
> And this one as 'sleep_l'.

Actually, I do see this as "VOL Down". So ignore that and I assume we
re-use recovery so ...

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 07/11] arm64: tegra: Enable SDHCI controllers on P3110

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 4294 bytes --]

On Wed, Mar 08, 2017 at 11:46:10AM +0000, Jon Hunter wrote:
> 
> On 23/02/17 17:30, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > The P3110 processor module wires one of the SDHCI controllers to an on-
> > board eMMC and exposes another set of SD/MMC signals on the connector to
> > support an external SD/MMC card. A third controller is connected to the
> > SDIO pins of an M.2 KEY E connector.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 42 ++++++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > index 1a9ac73b4ecb..b18e166527d8 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > @@ -7,6 +7,8 @@
> >  	compatible = "nvidia,p3310", "nvidia,tegra186";
> >  
> >  	aliases {
> > +		sdhci0 = "/sdhci@3460000";
> > +		sdhci1 = "/sdhci@3400000";
> 
> Any reason why you don't include all 3 sdhci controllers here?

It turns out this is completely useless. The intention had been to make
sdhci@3460000 appear as mmc0 and sdhci@3400000 as mmc1 in order to give
a more natural ordering (built-in eMMC first, then external SD/MMC) but
there's no code in the kernel that will enforce this.

This is also the reason why sdhci@3440000 is not included in this list
because it connects to a WIFI/Bluetooth module.

I'm slightly leaning towards leaving this in and possibly write a patch
to enforce ordering as given by the aliases. Of course nobody in their
right mind should be depending on the device names remaining the same
and use partition UUIDs or labels instead. But having enforcing the
order would still provide the least surprise.

> 
> >  		serial0 = &uarta;
> >  		i2c0 = "/bpmp/i2c";
> >  		i2c1 = "/i2c@3160000";
> > @@ -72,6 +74,32 @@
> >  		status = "okay";
> >  	};
> >  
> > +	/* SDMMC1 (SD/MMC) */
> > +	sdhci@3400000 {
> > +		status = "okay";
> > +
> > +		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>;
> 
> I see the CD as P-5 and not P-6 on the schematic.

Urgh... I probably mixed these up by looking at the Parker datasheet
(not sure if that's publicly available yet) and that says PP.05 actually
has the SDMMC3_CD special function. But since these are used as plain
GPIOs that's not where the function is defined. And indeed I see that
the schematics has PP.05 as the CD for SDMMC1.

Strangely I remember card-detect working with the above...

> > +		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
> > +
> > +		vqmmc-supply = <&vddio_sdmmc1>;
> > +		vmmc-supply = <&vdd_sd>;
> 
> The card slot is on the carrier board and although the cd and wp pins
> are allocated on the cvm, I did not see a reference to the vmmc-supply
> on the cvm. So should the 'vmmc-supply' be in the carrier board file?

Yes, I think it's best to move vmmc-supply to the P2771 board file...

> 
> > +	};
> > +
> > +	/* SDMMC3 (SDIO) */
> > +	sdhci@3440000 {
> > +		status = "okay";
> > +	};
> > +
> > +	/* SDMMC4 (eMMC) */
> > +	sdhci@3460000 {
> > +		status = "okay";
> > +		bus-width = <8>;
> > +		non-removable;
> > +
> > +		vqmmc-supply = <&vdd_1v8_ap>;
> > +		vmmc-supply = <&vdd_3v3_sys>;
> > +	};
> > +
> >  	hsp@3c00000 {
> >  		status = "okay";
> >  	};
> > @@ -333,5 +361,19 @@
> >  
> >  			vin-supply = <&vdd_1v8>;
> >  		};
> > +
> > +		vdd_sd: regulator@2 {
> > +			compatible = "regulator-fixed";
> > +			reg = <2>;
> > +
> > +			regulator-name = "SD_CARD_SW_PWR";
> > +			regulator-min-microvolt = <3300000>;
> > +			regulator-max-microvolt = <3300000>;
> > +
> > +			gpio = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
> 
> Here I see the gpio as P-6 and not P-5.

Yes, that also matches the schematics that I have. Strange how this
would still all work given the mixup...

> > +			enable-active-high;
> > +
> > +			vin-supply = <&vdd_3v3_sys>;
> > +		};
> >  	};
> >  };
> 
> I also see the above regulator on the carrier board and not on the cvm.

... and move this to the P2771 board file as well.

Thanks,
Thierry

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2] arm64: tegra: Add initial power tree for P3310

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed
regulators to model the power tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- update LDO7 and LDO8 for C03 revision (Jon Hunter)

 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 220 +++++++++++++++++++++++++
 1 file changed, 220 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index ffbb4be5122e..69553bde7ef7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -1,5 +1,7 @@
 #include "tegra186.dtsi"
 
+#include <dt-bindings/mfd/max77620.h>
+
 / {
 	model = "NVIDIA Tegra186 P3310 Processor Module";
 	compatible = "nvidia,p3310", "nvidia,tegra186";
@@ -115,6 +117,189 @@
 	bpmp {
 		i2c {
 			status = "okay";
+
+			pmic: pmic@3c {
+				compatible = "maxim,max77620";
+				reg = <0x3c>;
+
+				interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+
+				#gpio-cells = <2>;
+				gpio-controller;
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&max77620_default>;
+
+				max77620_default: pinmux {
+					gpio0 {
+						pins = "gpio0";
+						function = "gpio";
+					};
+
+					gpio1 {
+						pins = "gpio1";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+					};
+
+					gpio2 {
+						pins = "gpio2";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+					};
+
+					gpio3 {
+						pins = "gpio3";
+						function = "fps-out";
+						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+					};
+
+					gpio4 {
+						pins = "gpio4";
+						function = "32k-out1";
+						drive-push-pull = <1>;
+					};
+
+					gpio5 {
+						pins = "gpio5";
+						function = "gpio";
+						drive-push-pull = <0>;
+					};
+
+					gpio6 {
+						pins = "gpio6";
+						function = "gpio";
+						drive-push-pull = <1>;
+					};
+
+					gpio7 {
+						pins = "gpio7";
+						function = "gpio";
+						drive-push-pull = <0>;
+					};
+				};
+
+				fps {
+					fps0 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+
+					fps1 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+
+					fps2 {
+						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+						maxim,shutdown-fps-time-period-us = <640>;
+					};
+				};
+
+				regulators {
+					in-sd0-supply = <&vdd_5v0_sys>;
+					in-sd1-supply = <&vdd_5v0_sys>;
+					in-sd2-supply = <&vdd_5v0_sys>;
+					in-sd3-supply = <&vdd_5v0_sys>;
+
+					in-ldo0-1-supply = <&vdd_5v0_sys>;
+					in-ldo2-supply = <&vdd_5v0_sys>;
+					in-ldo3-5-supply = <&vdd_5v0_sys>;
+					in-ldo4-6-supply = <&vdd_1v8>;
+					in-ldo7-8-supply = <&avdd_dsi_csi>;
+
+					sd0 {
+						regulator-name = "VDD_DDR_1V1_PMIC";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <1100000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					avdd_dsi_csi: sd1 {
+						regulator-name = "AVDD_DSI_CSI_1V2";
+						regulator-min-microvolt = <1200000>;
+						regulator-max-microvolt = <1200000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_1v8: sd2 {
+						regulator-name = "VDD_1V8";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_3v3_sys: sd3 {
+						regulator-name = "VDD_3V3_SYS";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					ldo0 {
+						regulator-name = "VDD_1V8_AP_PLL";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					ldo2 {
+						regulator-name = "VDDIO_3V3_AOHV";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vddio_sdmmc1: ldo3 {
+						regulator-name = "VDDIO_SDMMC1_AP";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <3300000>;
+					};
+
+					ldo4 {
+						regulator-name = "VDD_RTC";
+						regulator-min-microvolt = <1000000>;
+						regulator-max-microvolt = <1000000>;
+					};
+
+					vddio_sdmmc3: ldo5 {
+						regulator-name = "VDDIO_SDMMC3_AP";
+						regulator-min-microvolt = <2800000>;
+						regulator-max-microvolt = <2800000>;
+					};
+
+					vdd_hdmi: ldo7 {
+						regulator-name = "VDD_HDMI_1V05";
+						regulator-min-microvolt = <1050000>;
+						regulator-max-microvolt = <1050000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_pex: ldo8 {
+						regulator-name = "VDD_PEX_1V05";
+						regulator-min-microvolt = <1050000>
+						regulator-max-microvolt = <1050000>;
+						/* XXX */
+						regulator-always-on;
+						regulator-boot-on;
+					};
+				};
+			};
 		};
 	};
 
@@ -123,4 +308,39 @@
 		status = "okay";
 		method = "smc";
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_sys: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+
+			regulator-name = "VDD_5V0_SYS";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_1v8_ap: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+
+			regulator-name = "VDD_1V8_AP";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+
+			/* XXX */
+			regulator-always-on;
+			regulator-boot-on;
+
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+
+			vin-supply = <&vdd_1v8>;
+		};
+	};
 };
-- 
2.12.0

[PATCH v2 1/2] arm64: tegra: Enable SDHCI controllers on P3110

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The P3110 processor module wires one of the SDHCI controllers to an on-
board eMMC and exposes another set of SD/MMC signals on the connector to
support an external SD/MMC card. A third controller is connected to the
SDIO pins of an M.2 KEY E connector.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- move SD_CARD_SW_PWR regulator to carrier board (separate patch)
- move status = "okay" to carrier board
- fix card-detect GPIO for SDMMC1

 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 69553bde7ef7..847e7db59b47 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -7,6 +7,8 @@
 	compatible = "nvidia,p3310", "nvidia,tegra186";
 
 	aliases {
+		sdhci0 = "/sdhci@3460000";
+		sdhci1 = "/sdhci@3400000";
 		serial0 = &uarta;
 		i2c0 = "/bpmp/i2c";
 		i2c1 = "/i2c@3160000";
@@ -72,6 +74,29 @@
 		status = "okay";
 	};
 
+	/* SDMMC1 (SD/MMC) */
+	sdhci@3400000 {
+		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
+
+		vqmmc-supply = <&vddio_sdmmc1>;
+	};
+
+	/* SDMMC3 (SDIO) */
+	sdhci@3440000 {
+		status = "okay";
+	};
+
+	/* SDMMC4 (eMMC) */
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vqmmc-supply = <&vdd_1v8_ap>;
+		vmmc-supply = <&vdd_3v3_sys>;
+	};
+
 	hsp@3c00000 {
 		status = "okay";
 	};
-- 
2.12.0

[PATCH v2 2/2] arm64: tegra: Enable SD/MMC slot on P2771

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The P3310 processor module makes provisions for exposing the SDMMC1
controller via a standard SD/MMC slot, which the P2771 supports. Hook
up the power supply provided on the P2771 carrier board and enable
the device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- new patch

 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 0d3c0996d832..b80c1c3483db 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -5,4 +5,27 @@
 / {
 	model = "NVIDIA Tegra186 P2771-0000 Development Board";
 	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	/* SDMMC1 (SD/MMC) */
+	sdhci@3400000 {
+		status = "okay";
+
+		vmmc-supply = <&vdd_sd>;
+	};
+
+	regulators {
+		vdd_sd: regulator@100 {
+			compatible = "regulator-fixed";
+			reg = <100>;
+
+			regulator-name = "SD_CARD_SW_PWR";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+
+			gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+
+			vin-supply = <&vdd_3v3_sys>;
+		};
+	};
 };
-- 
2.12.0

Re: [PATCH 09/11] arm64: tegra: Add GPIO keys on P2771

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 2643 bytes --]

On Wed, Mar 08, 2017 at 12:15:53PM +0000, Jon Hunter wrote:
> 
> On 08/03/17 12:03, Jon Hunter wrote:
> > 
> > 
> > On 23/02/17 17:30, Thierry Reding wrote:
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> The P2771 has three keys (power, volume up and volume down) that are
> >> connected to pins on the AON GPIO controller.
> >>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 34 ++++++++++++++++++++++
> >>  1 file changed, 34 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> >> index 0d3c0996d832..1c195d71806d 100644
> >> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> >> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> >> @@ -1,8 +1,42 @@
> >>  /dts-v1/;
> >>  
> >> +#include <dt-bindings/input/linux-event-codes.h>
> >> +
> >>  #include "tegra186-p3310.dtsi"
> >>  
> >>  / {
> >>  	model = "NVIDIA Tegra186 P2771-0000 Development Board";
> >>  	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
> >> +
> >> +	gpio-keys {
> >> +		compatible = "gpio-keys";
> >> +
> >> +		power {
> >> +			label = "Power";
> >> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
> >> +					   GPIO_ACTIVE_LOW>;
> >> +			linux,input-type = <EV_KEY>;
> >> +			linux,code = <KEY_POWER>;
> >> +			debounce-interval = <10>;
> >> +			wakeup-source;
> >> +		};
> >> +
> >> +		volume-up {
> >> +			label = "Volume Up";
> >> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
> >> +					   GPIO_ACTIVE_LOW>;
> >> +			linux,input-type = <EV_KEY>;
> >> +			linux,code = <KEY_VOLUMEUP>;
> >> +			debounce-interval = <10>;
> >> +		};
> > 
> > My schematic shows this pin as 'force-recovery'.
> > 
> >> +
> >> +		volume-down {
> >> +			label = "Volume Down";
> >> +			gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
> >> +					   GPIO_ACTIVE_LOW>;
> >> +			linux,input-type = <EV_KEY>;
> >> +			linux,code = <KEY_VOLUMEDOWN>;
> >> +			debounce-interval = <10>;
> >> +		};
> >> +	};
> >>  };
> > 
> > And this one as 'sleep_l'.
> 
> Actually, I do see this as "VOL Down". So ignore that and I assume we
> re-use recovery so ...
> 
> Acked-by: Jon Hunter <jonathanh@nvidia.com>

Yes, the board marks FF.02 as "VOL D" and I figured that recovery isn't
useful during normal system operation and "VOL U" would be the natural
choice. Often these keys end up being used for menu navigation in some
Android bootloader. That's not relevant to Linux, but it gives us some
consistency across the board.

Thierry

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2] arm64: tegra: Add initial power tree for P3310

[Jon Hunter]

On 08/03/17 13:24, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed
> regulators to model the power tree.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - update LDO7 and LDO8 for C03 revision (Jon Hunter)
> 
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 220 +++++++++++++++++++++++++
>  1 file changed, 220 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index ffbb4be5122e..69553bde7ef7 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -1,5 +1,7 @@
>  #include "tegra186.dtsi"
>  
> +#include <dt-bindings/mfd/max77620.h>
> +
>  / {
>  	model = "NVIDIA Tegra186 P3310 Processor Module";
>  	compatible = "nvidia,p3310", "nvidia,tegra186";
> @@ -115,6 +117,189 @@
>  	bpmp {
>  		i2c {
>  			status = "okay";
> +
> +			pmic: pmic@3c {
> +				compatible = "maxim,max77620";
> +				reg = <0x3c>;
> +
> +				interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> +				#interrupt-cells = <2>;
> +				interrupt-controller;
> +
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&max77620_default>;
> +
> +				max77620_default: pinmux {
> +					gpio0 {
> +						pins = "gpio0";
> +						function = "gpio";
> +					};
> +
> +					gpio1 {
> +						pins = "gpio1";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
> +					};
> +
> +					gpio2 {
> +						pins = "gpio2";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
> +					};
> +
> +					gpio3 {
> +						pins = "gpio3";
> +						function = "fps-out";
> +						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
> +					};
> +
> +					gpio4 {
> +						pins = "gpio4";
> +						function = "32k-out1";
> +						drive-push-pull = <1>;
> +					};
> +
> +					gpio5 {
> +						pins = "gpio5";
> +						function = "gpio";
> +						drive-push-pull = <0>;
> +					};
> +
> +					gpio6 {
> +						pins = "gpio6";
> +						function = "gpio";
> +						drive-push-pull = <1>;
> +					};
> +
> +					gpio7 {
> +						pins = "gpio7";
> +						function = "gpio";
> +						drive-push-pull = <0>;
> +					};
> +				};
> +
> +				fps {
> +					fps0 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +
> +					fps1 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +
> +					fps2 {
> +						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
> +						maxim,shutdown-fps-time-period-us = <640>;
> +					};
> +				};
> +
> +				regulators {
> +					in-sd0-supply = <&vdd_5v0_sys>;
> +					in-sd1-supply = <&vdd_5v0_sys>;
> +					in-sd2-supply = <&vdd_5v0_sys>;
> +					in-sd3-supply = <&vdd_5v0_sys>;
> +
> +					in-ldo0-1-supply = <&vdd_5v0_sys>;
> +					in-ldo2-supply = <&vdd_5v0_sys>;
> +					in-ldo3-5-supply = <&vdd_5v0_sys>;
> +					in-ldo4-6-supply = <&vdd_1v8>;
> +					in-ldo7-8-supply = <&avdd_dsi_csi>;
> +
> +					sd0 {
> +						regulator-name = "VDD_DDR_1V1_PMIC";
> +						regulator-min-microvolt = <1100000>;
> +						regulator-max-microvolt = <1100000>;
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					avdd_dsi_csi: sd1 {
> +						regulator-name = "AVDD_DSI_CSI_1V2";
> +						regulator-min-microvolt = <1200000>;
> +						regulator-max-microvolt = <1200000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vdd_1v8: sd2 {
> +						regulator-name = "VDD_1V8";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <1800000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vdd_3v3_sys: sd3 {
> +						regulator-name = "VDD_3V3_SYS";
> +						regulator-min-microvolt = <3300000>;
> +						regulator-max-microvolt = <3300000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					ldo0 {
> +						regulator-name = "VDD_1V8_AP_PLL";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <1800000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					ldo2 {
> +						regulator-name = "VDDIO_3V3_AOHV";
> +						regulator-min-microvolt = <3300000>;
> +						regulator-max-microvolt = <3300000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vddio_sdmmc1: ldo3 {
> +						regulator-name = "VDDIO_SDMMC1_AP";
> +						regulator-min-microvolt = <1800000>;
> +						regulator-max-microvolt = <3300000>;
> +					};
> +
> +					ldo4 {
> +						regulator-name = "VDD_RTC";
> +						regulator-min-microvolt = <1000000>;
> +						regulator-max-microvolt = <1000000>;
> +					};
> +
> +					vddio_sdmmc3: ldo5 {
> +						regulator-name = "VDDIO_SDMMC3_AP";
> +						regulator-min-microvolt = <2800000>;
> +						regulator-max-microvolt = <2800000>;
> +					};
> +
> +					vdd_hdmi: ldo7 {
> +						regulator-name = "VDD_HDMI_1V05";
> +						regulator-min-microvolt = <1050000>;
> +						regulator-max-microvolt = <1050000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +
> +					vdd_pex: ldo8 {
> +						regulator-name = "VDD_PEX_1V05";
> +						regulator-min-microvolt = <1050000>
> +						regulator-max-microvolt = <1050000>;
> +						/* XXX */
> +						regulator-always-on;
> +						regulator-boot-on;
> +					};
> +				};
> +			};
>  		};
>  	};
>  
> @@ -123,4 +308,39 @@
>  		status = "okay";
>  		method = "smc";
>  	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		vdd_5v0_sys: regulator@0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +
> +			regulator-name = "VDD_5V0_SYS";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +		};
> +
> +		vdd_1v8_ap: regulator@1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +
> +			regulator-name = "VDD_1V8_AP";
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +
> +			/* XXX */
> +			regulator-always-on;
> +			regulator-boot-on;
> +
> +			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +
> +			vin-supply = <&vdd_1v8>;
> +		};
> +	};
>  };
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH v2 1/2] arm64: tegra: Enable SDHCI controllers on P3110

[Jon Hunter]

On 08/03/17 13:39, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The P3110 processor module wires one of the SDHCI controllers to an on-
> board eMMC and exposes another set of SD/MMC signals on the connector to
> support an external SD/MMC card. A third controller is connected to the
> SDIO pins of an M.2 KEY E connector.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - move SD_CARD_SW_PWR regulator to carrier board (separate patch)
> - move status = "okay" to carrier board
> - fix card-detect GPIO for SDMMC1
> 
>  arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 69553bde7ef7..847e7db59b47 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -7,6 +7,8 @@
>  	compatible = "nvidia,p3310", "nvidia,tegra186";
>  
>  	aliases {
> +		sdhci0 = "/sdhci@3460000";
> +		sdhci1 = "/sdhci@3400000";
>  		serial0 = &uarta;
>  		i2c0 = "/bpmp/i2c";
>  		i2c1 = "/i2c@3160000";
> @@ -72,6 +74,29 @@
>  		status = "okay";
>  	};
>  
> +	/* SDMMC1 (SD/MMC) */
> +	sdhci@3400000 {
> +		cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
> +		wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
> +
> +		vqmmc-supply = <&vddio_sdmmc1>;
> +	};
> +
> +	/* SDMMC3 (SDIO) */
> +	sdhci@3440000 {
> +		status = "okay";
> +	};
> +
> +	/* SDMMC4 (eMMC) */
> +	sdhci@3460000 {
> +		status = "okay";
> +		bus-width = <8>;
> +		non-removable;
> +
> +		vqmmc-supply = <&vdd_1v8_ap>;
> +		vmmc-supply = <&vdd_3v3_sys>;
> +	};
> +
>  	hsp@3c00000 {
>  		status = "okay";
>  	};

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

Re: [PATCH v2 2/2] arm64: tegra: Enable SD/MMC slot on P2771

[Jon Hunter]

On 08/03/17 13:39, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> The P3310 processor module makes provisions for exposing the SDMMC1
> controller via a standard SD/MMC slot, which the P2771 supports. Hook
> up the power supply provided on the P2771 carrier board and enable
> the device tree node.
> 
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> Changes in v2:
> - new patch
> 
>  arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 0d3c0996d832..b80c1c3483db 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -5,4 +5,27 @@
>  / {
>  	model = "NVIDIA Tegra186 P2771-0000 Development Board";
>  	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
> +
> +	/* SDMMC1 (SD/MMC) */
> +	sdhci@3400000 {
> +		status = "okay";
> +
> +		vmmc-supply = <&vdd_sd>;
> +	};
> +
> +	regulators {
> +		vdd_sd: regulator@100 {
> +			compatible = "regulator-fixed";
> +			reg = <100>;
> +
> +			regulator-name = "SD_CARD_SW_PWR";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +
> +			gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +
> +			vin-supply = <&vdd_3v3_sys>;
> +		};
> +	};
>  };

Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Cheers
Jon

-- 
nvpublic

Re: [PATCH 01/11] arm64: tegra: Add PMC controller on Tegra186

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 385 bytes --]

On Thu, Feb 23, 2017 at 06:30:43PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)

Applied all of these to for-4.12/arm64/dt.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]