From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH] drm/tegra: add tiling FB modifiers Date: Mon, 20 Mar 2017 18:26:35 +0100 Message-ID: <20170320172635.GD14787@ulmo.ba.sec> References: <20161108075042.13357-1-acourbot@nvidia.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0698304068==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Alexandre Courbot Cc: Alexandre Courbot , linux-kernel@vger.kernel.org, "dri-devel@lists.freedesktop.org" , "linux-tegra@vger.kernel.org" List-Id: linux-tegra@vger.kernel.org --===============0698304068== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="C+ts3FVlLX8+P6JN" Content-Disposition: inline --C+ts3FVlLX8+P6JN Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 08, 2016 at 06:19:01PM +0900, Alexandre Courbot wrote: > On 11/08/2016 06:07 PM, Erik Faye-Lund wrote: > > On Tue, Nov 8, 2016 at 8:50 AM, Alexandre Courbot = wrote: > >> Add FB modifiers to allow user-space to specify that a surface is in o= ne > >> of the two tiling formats supported by Tegra chips, and add support in > >> the tegradrm driver to handle them properly. This is necessary for the > >> display controller to directly display buffers generated by the GPU. > >> > >> This feature is intended to replace the dedicated IOCTL enabled > >> by TEGRA_STAGING and to provide a non-staging alternative to that > >> solution. > >> > >> Signed-off-by: Alexandre Courbot > >> --- > >> drivers/gpu/drm/tegra/drm.c | 2 ++ > >> drivers/gpu/drm/tegra/fb.c | 23 +++++++++++++++++++--- > >> include/uapi/drm/drm_fourcc.h | 45 ++++++++++++++++++++++++++++++++++= +++++++++ > >> 3 files changed, 67 insertions(+), 3 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c > >> index a9630c2d6cb3..36b4b30a5164 100644 > >> --- a/drivers/gpu/drm/tegra/drm.c > >> +++ b/drivers/gpu/drm/tegra/drm.c > >> @@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, = unsigned long flags) > >> drm->mode_config.max_width =3D 4096; > >> drm->mode_config.max_height =3D 4096; > >> > >> + drm->mode_config.allow_fb_modifiers =3D true; > >> + > >> drm->mode_config.funcs =3D &tegra_drm_mode_funcs; > >> > >> err =3D tegra_drm_fb_prepare(drm); > >> diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c > >> index e6d71fa4028e..2fded58b2ca5 100644 > >> --- a/drivers/gpu/drm/tegra/fb.c > >> +++ b/drivers/gpu/drm/tegra/fb.c > >> @@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *fra= mebuffer, > >> struct tegra_bo_tiling *tiling) > >> { > >> struct tegra_fb *fb =3D to_tegra_fb(framebuffer); > >> - > >> - /* TODO: handle YUV formats? */ > >> - *tiling =3D fb->planes[0]->tiling; > >> + uint64_t modifier =3D fb->base.modifier[0]; > >> + > >> + switch (fourcc_mod_tegra_mod(modifier)) { > >> + case NV_FORMAT_MOD_TEGRA_TILED: > >> + tiling->mode =3D TEGRA_BO_TILING_MODE_TILED; > >> + tiling->value =3D 0; > >> + break; > >> + > >> + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): > >> + tiling->mode =3D TEGRA_BO_TILING_MODE_BLOCK; > >> + tiling->value =3D fourcc_mod_tegra_param(modifier); > >> + if (tiling->value > 5) > >> + return -EINVAL; > >=20 > > Shouldn't this contain some hardware-check for the support? AFAIK, not > > all Tegras support all block-heights (if even this mode at all?)... >=20 > tegra_dc_setup_window does that check later (check the test on > dc->soc->supports_block_linear). At the moment no error message is > displayed though (and it seems like we are writing a stale value in > DC_WIN_BUFFER_ADDR_MODE if the SoC doesn't support block linear and the > tiling mode is TEGRA_BO_TILING_MODE_BLOCK?) tegra_plane_atomic_check() has a check for this, as well as an error message. ->atomic_check() will always run before actually setting the mode, or applying the plane state, so it effectively guards against a user specifying a format that the hardware doesn't support. Thierry --C+ts3FVlLX8+P6JN Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljQEMcACgkQ3SOs138+ s6ECcA/+McKwbWkRZ/JWUcV8JT8dV5/N0CRul6KVkJ2eZiz9zfHR1mzfKMC9WZbC lqwc2PR8zePxy6OJqlMtBUDTc7WjE9qolQlnW6cHPuAlB1f2osBtNkrSy1y+8vNo Zbbs/lyR8GndeE/nSG6eKOVKfzpXp9Z2+4Oi/jma25TPa8Bg3xe17lShlDmGlEzS pkG/oukX1SjLcCRQjCzqpnOhuskBuORRsmp3jsu/d+NB0hqltVGDDelk7JYUBgH8 GPKPRRH/RVohD6awm+3Grb8i+jLCJ1fmFFU5xxicvAr5H5lDvYrQxx4vLo01VUEW iupMb1IxyhbM+pqXGj33cYQeC23WBUtXXGR16MxyehJk4GI4FMd3PhYrMaXq+Lkz Mx6wU0wTh1Vdsz8wwXxqtdbEuggEgJq6kKwTkuxUpA1nlFTFmAnIiG4Mf9Du1Tog hTrq/IG/gYHV/ZWuAAghU2y+reC+6p+JTVucmN1NZd4DBY7NakUM3I3WNdoiOVnZ 1qErEHaT/xLvE9Nqjmh8eTIZxp4oud5hSrOmXPa1R9/cYuTEkEn7HZFx9FPKowxg hsWrcSPCfOSdXUEL74DbXHJTpGTUECaca96zM/3CVbpyZLZ3Zskgwwk1W+EZiQdc dd469xWs8SxjIrS9L0583GR084dmsb8vaTMZjzuWwMN5YOxmqjw= =bE3y -----END PGP SIGNATURE----- --C+ts3FVlLX8+P6JN-- --===============0698304068== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============0698304068==--