From: Thierry Reding <thierry.reding@gmail.com>
To: Laxman Dewangan <ldewangan@nvidia.com>
Cc: jonathanh@nvidia.com, linux-pwm@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
Date: Tue, 13 Jun 2017 14:32:42 +0200 [thread overview]
Message-ID: <20170613123242.GA16758@ulmo.fritz.box> (raw)
In-Reply-To: <1493733937-15822-1-git-send-email-ldewangan@nvidia.com>
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On Tue, May 02, 2017 at 07:35:37PM +0530, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> Before Tegra186, it is 38.4MHz.
> In Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency to the maximum IP
> supported frequency. Provide these values via SoC chipdata.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>
> ---
> Changes from V1:
> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> - Set the maximum frequency unconditionally as per V1 review comment.
> ---
> drivers/pwm/pwm-tegra.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
Applied with a fixed up commit message and Jon's Acked-by.
Thanks,
Thierry
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prev parent reply other threads:[~2017-06-13 12:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-02 14:05 [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout Laxman Dewangan
[not found] ` <1493733937-15822-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 15:23 ` Jon Hunter
[not found] ` <908ed0dc-2a75-4348-357c-191fa7348974-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 17:43 ` Laxman Dewangan
[not found] ` <5908C555.7090204-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 20:10 ` Jon Hunter
2017-05-15 15:17 ` Laxman Dewangan
2017-06-13 12:32 ` Thierry Reding [this message]
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