From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Subject: Re: [PATCH v2 1/4] clk: tegra: Add la clock for Tegra210
Date: Thu, 21 Dec 2017 11:00:52 +0200
Message-ID: <20171221090052.GR29417@tbergstrom-lnx.Nvidia.com>
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To: Jon Hunter <jonathanh@nvidia.com>
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On Tue, Dec 19, 2017 at 11:00:52PM +0000, Jon Hunter wrote:
> 
> On 16/11/17 14:28, Peter De Schrijver wrote:
> > This clock is needed by the memory built-in self test work around.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  drivers/clk/tegra/clk-tegra210.c         | 12 ++++++++++++
> >  include/dt-bindings/clock/tegra210-car.h |  2 +-
> >  2 files changed, 13 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> > index 6d7a613..55a5b7f 100644
> > --- a/drivers/clk/tegra/clk-tegra210.c
> > +++ b/drivers/clk/tegra/clk-tegra210.c
> > @@ -40,6 +40,7 @@
> >  
> >  #define CLK_SOURCE_CSITE 0x1d4
> >  #define CLK_SOURCE_EMC 0x19c
> > +#define CLK_SOURCE_LA 0x1f8
> >  
> >  #define PLLC_BASE 0x80
> >  #define PLLC_OUT 0x84
> > @@ -2628,6 +2629,13 @@ static int tegra210_init_pllu(void)
> >  	return 0;
> >  }
> >  
> > +static const char * const la_parents[] = {
> > +	"pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
> > +};
> > +
> > +static struct tegra_clk_periph tegra210_la =
> > +	TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
> > +
> 
> The above are over 80 characters. I know we already have some in this
> file that are, but we should avoid it where we can.

la_parents could be split, but I don't think it's any more clear if tegra210_la is split.

Peter.