[PATCH v1 0/3] CPU clock changes for Tegra20/30

[PATCH v1 0/3] CPU clock changes for Tegra20/30

[Dmitry Osipenko]

Hello,

This series is a prerequisite for the CPUFREQ driver patches, it can be
applied separately. CPUFREQ will be supported on Tegra30 once this and
the CPUFREQ patch-series will be applied.

Dmitry Osipenko (3):
  clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30
  clk: tegra: Add more rates to Tegra30 PLLX frequency table
  clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30

 drivers/clk/tegra/clk-super.c    |  16 +++-
 drivers/clk/tegra/clk-tegra20.c  |  51 ++++++++++--
 drivers/clk/tegra/clk-tegra210.c |   2 +-
 drivers/clk/tegra/clk-tegra30.c  | 131 +++++++++++++++++++++----------
 drivers/clk/tegra/clk.h          |   9 ++-
 5 files changed, 156 insertions(+), 53 deletions(-)

-- 
2.18.0

[PATCH v1 1/3] clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30

[Dmitry Osipenko]

Some of the CCLKG parents aren't accessible via device tree because they
are created as non-DT clocks. Apparently there is no reason to define
these clocks in that manner, hence convert CCLKG mux to mux + clock
divider to remove the non-DT parent clocks. Now it is possible to request
all of CCLKG parents from device tree, which is necessary for the CPUFreq
driver.

Note that CCLKG bypasses clock divider only if PLLX is selected as the
parent, hence previous CCLKG parents definition was incorrect.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/clk/tegra/clk-super.c    | 16 +++++++++++++-
 drivers/clk/tegra/clk-tegra210.c |  2 +-
 drivers/clk/tegra/clk-tegra30.c  | 38 +++++---------------------------
 drivers/clk/tegra/clk.h          |  9 ++++++--
 4 files changed, 28 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 84267cfc4433..8ba58f7942d9 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -65,6 +65,8 @@ static u8 clk_super_get_parent(struct clk_hw *hw)
 	    (source == mux->pllx_index))
 		source = mux->div2_index;
 
+	mux->pllx_parent = (source == mux->pllx_index);
+
 	return source;
 }
 
@@ -114,6 +116,8 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
 	writel_relaxed(val, mux->reg);
 	udelay(2);
 
+	mux->pllx_parent = (index == mux->pllx_index);
+
 out:
 	if (mux->lock)
 		spin_unlock_irqrestore(mux->lock, flags);
@@ -132,6 +136,9 @@ static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
 	struct clk_hw *div_hw = &super->frac_div.hw;
 
+	if ((super->flags & TEGRA_CCLKG_DIVIDER) && super->pllx_parent)
+		return *parent_rate;
+
 	__clk_hw_set_clk(div_hw, hw);
 
 	return super->div_ops->round_rate(div_hw, rate, parent_rate);
@@ -143,6 +150,9 @@ static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
 	struct clk_hw *div_hw = &super->frac_div.hw;
 
+	if ((super->flags & TEGRA_CCLKG_DIVIDER) && super->pllx_parent)
+		return parent_rate;
+
 	__clk_hw_set_clk(div_hw, hw);
 
 	return super->div_ops->recalc_rate(div_hw, parent_rate);
@@ -154,6 +164,9 @@ static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
 	struct clk_hw *div_hw = &super->frac_div.hw;
 
+	if ((super->flags & TEGRA_CCLKG_DIVIDER) && super->pllx_parent)
+		return 0;
+
 	__clk_hw_set_clk(div_hw, hw);
 
 	return super->div_ops->set_rate(div_hw, rate, parent_rate);
@@ -204,7 +217,7 @@ struct clk *tegra_clk_register_super_mux(const char *name,
 }
 
 struct clk *tegra_clk_register_super_clk(const char *name,
-		const char * const *parent_names, u8 num_parents,
+		const char * const *parent_names, u8 num_parents, u8 pllx_index,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		spinlock_t *lock)
 {
@@ -232,6 +245,7 @@ struct clk *tegra_clk_register_super_clk(const char *name,
 	super->frac_div.frac_width = 1;
 	super->frac_div.lock = lock;
 	super->div_ops = &tegra_clk_frac_div_ops;
+	super->pllx_index = pllx_index;
 
 	/* Data in .init is copied by clk_register(), so stack variable OK */
 	super->hw.init = &init;
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9eb1cb14fce1..990c8773e50c 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3026,7 +3026,7 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
 	clks[TEGRA210_CLK_CML1] = clk;
 
 	clk = tegra_clk_register_super_clk("aclk", aclk_parents,
-				ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
+				ARRAY_SIZE(aclk_parents), 0, 0, clk_base + 0x6e0,
 				0, NULL);
 	clks[TEGRA210_CLK_ACLK] = clk;
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index acfe661b2ae7..c4b78316ba8a 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -902,8 +902,8 @@ static void __init tegra30_pll_init(void)
 }
 
 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-					"pll_p_cclkg", "pll_p_out4_cclkg",
-					"pll_p_out3_cclkg", "unused", "pll_x" };
+					"pll_p", "pll_p_out4", "pll_p_out3",
+					"unused", "pll_x" };
 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
 					 "pll_p_cclklp", "pll_p_out4_cclklp",
 					 "pll_p_out3_cclklp", "unused", "pll_x",
@@ -916,39 +916,11 @@ static void __init tegra30_super_clk_init(void)
 {
 	struct clk *clk;
 
-	/*
-	 * Clock input to cclk_g divided from pll_p using
-	 * U71 divider of cclk_g.
-	 */
-	clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
-				clk_base + SUPER_CCLKG_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_cclkg", NULL);
-
-	/*
-	 * Clock input to cclk_g divided from pll_p_out3 using
-	 * U71 divider of cclk_g.
-	 */
-	clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
-				clk_base + SUPER_CCLKG_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
-
-	/*
-	 * Clock input to cclk_g divided from pll_p_out4 using
-	 * U71 divider of cclk_g.
-	 */
-	clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
-				clk_base + SUPER_CCLKG_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
-
 	/* CCLKG */
-	clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
-				  ARRAY_SIZE(cclk_g_parents),
-				  CLK_SET_RATE_PARENT,
+	clk = tegra_clk_register_super_clk("cclk_g", cclk_g_parents,
+				  ARRAY_SIZE(cclk_g_parents), 8, 0,
 				  clk_base + CCLKG_BURST_POLICY,
-				  0, 4, 0, 0, NULL);
+				  TEGRA_CCLKG_DIVIDER, NULL);
 	clks[TEGRA30_CLK_CCLK_G] = clk;
 
 	/*
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index d2c3a010f8e9..64922f0f5fdd 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -680,6 +680,9 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
  * Flags:
  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
  *     that this is LP cluster clock.
+ *
+ * TEGRA_CCLKG_DIVIDER - G cluster clock may bypass clocks divider. This flag
+ *     indicates that this is G cluster clock.
  */
 struct tegra_clk_super_mux {
 	struct clk_hw	hw;
@@ -691,11 +694,13 @@ struct tegra_clk_super_mux {
 	u8		div2_index;
 	u8		pllx_index;
 	spinlock_t	*lock;
+	bool		pllx_parent;
 };
 
 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
 
-#define TEGRA_DIVIDER_2 BIT(0)
+#define TEGRA_DIVIDER_2		BIT(0)
+#define TEGRA_CCLKG_DIVIDER	BIT(1)
 
 extern const struct clk_ops tegra_clk_super_ops;
 struct clk *tegra_clk_register_super_mux(const char *name,
@@ -703,7 +708,7 @@ struct clk *tegra_clk_register_super_mux(const char *name,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
 struct clk *tegra_clk_register_super_clk(const char *name,
-		const char * const *parent_names, u8 num_parents,
+		const char * const *parent_names, u8 num_parents, u8 pllx_index,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		spinlock_t *lock);
 
-- 
2.18.0

Re: [PATCH v1 1/3] clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30

[Jon Hunter]

On 30/08/2018 20:20, Dmitry Osipenko wrote:
> Some of the CCLKG parents aren't accessible via device tree because they
> are created as non-DT clocks. Apparently there is no reason to define
> these clocks in that manner, hence convert CCLKG mux to mux + clock
> divider to remove the non-DT parent clocks. Now it is possible to request
> all of CCLKG parents from device tree, which is necessary for the CPUFreq
> driver.

Is it likely that all of these clock parents will be used by the CPUFreq
driver for these devices? If the clocks you currently need are available
then my preference would be to stick with what we have for now.

Cheers
Jon

-- 
nvpublic

Re: [PATCH v1 1/3] clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30

[Dmitry Osipenko]

On 10/17/18 11:53 AM, Jon Hunter wrote:
> 
> On 30/08/2018 20:20, Dmitry Osipenko wrote:
>> Some of the CCLKG parents aren't accessible via device tree because they
>> are created as non-DT clocks. Apparently there is no reason to define
>> these clocks in that manner, hence convert CCLKG mux to mux + clock
>> divider to remove the non-DT parent clocks. Now it is possible to request
>> all of CCLKG parents from device tree, which is necessary for the CPUFreq
>> driver.
> 
> Is it likely that all of these clock parents will be used by the CPUFreq
> driver for these devices? If the clocks you currently need are available
> then my preference would be to stick with what we have for now.

You could use them all if you want, that's what HW allow. The current clock description doesn't fully describe the HW, though it should be enough at least for the CPUFreq driver if we are going to use clk_get_sys() and stick to the "default" parent. Peter?

[PATCH v1 2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table

[Dmitry Osipenko]

Add more predefined rates to the PLLX table, allowing to lower the rate
down to 312MHz. This gives more variations of frequency selection to the
CPUFREQ driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/clk/tegra/clk-tegra30.c | 42 +++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c4b78316ba8a..0f8797ca39e2 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -342,6 +342,48 @@ static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 	{ 16800000, 1000000000,  833, 14, 1, 8 }, /* actual: 999.6 MHz */
 	{ 19200000, 1000000000,  625, 12, 1, 8 },
 	{ 26000000, 1000000000, 1000, 26, 1, 8 },
+	/* 912 MHz */
+	{ 12000000,  912000000,  912, 12, 1, 8 },
+	{ 13000000,  912000000,  912, 13, 1, 8 },
+	{ 16800000,  912000000,  760, 14, 1, 8 },
+	{ 19200000,  912000000,  760, 16, 1, 8 },
+	{ 26000000,  912000000,  912, 26, 1, 8 },
+	/* 816 MHz */
+	{ 12000000,  816000000,  816, 12, 1, 8 },
+	{ 13000000,  816000000,  816, 13, 1, 8 },
+	{ 16800000,  816000000,  680, 14, 1, 8 },
+	{ 19200000,  816000000,  680, 16, 1, 8 },
+	{ 26000000,  816000000,  816, 26, 1, 8 },
+	/* 760 MHz */
+	{ 12000000,  760000000,  760, 12, 1, 8 },
+	{ 13000000,  760000000,  760, 13, 1, 8 },
+	{ 16800000,  760000000,  950, 21, 1, 8 },
+	{ 19200000,  760000000,  950, 24, 1, 8 },
+	{ 26000000,  760000000,  760, 26, 1, 8 },
+	/* 750 MHz */
+	{ 12000000,  750000000,  750, 12, 1, 8 },
+	{ 13000000,  750000000,  750, 13, 1, 8 },
+	{ 16800000,  750000000,  625, 14, 1, 8 },
+	{ 19200000,  750000000,  625, 16, 1, 8 },
+	{ 26000000,  750000000,  750, 26, 1, 8 },
+	/* 608 MHz */
+	{ 12000000,  608000000,  608, 12, 1, 8 },
+	{ 13000000,  608000000,  608, 13, 1, 8 },
+	{ 16800000,  608000000,  760, 21, 1, 8 },
+	{ 19200000,  608000000,  380, 12, 1, 8 },
+	{ 26000000,  608000000,  608, 26, 1, 8 },
+	/* 456 MHz */
+	{ 12000000,  456000000,  456, 12, 1, 8 },
+	{ 13000000,  456000000,  456, 13, 1, 8 },
+	{ 16800000,  456000000,  380, 15, 1, 8 },
+	{ 19200000,  456000000,  380, 14, 1, 8 },
+	{ 26000000,  456000000,  456, 26, 1, 8 },
+	/* 312 MHz */
+	{ 12000000,  312000000,  312, 12, 1, 8 },
+	{ 13000000,  312000000,  312, 13, 1, 8 },
+	{ 16800000,  312000000,  260, 14, 1, 8 },
+	{ 19200000,  312000000,  260, 16, 1, 8 },
+	{ 26000000,  312000000,  312, 26, 1, 8 },
 	{        0,          0,    0,  0, 0, 0 },
 };
 
-- 
2.18.0

Re: [PATCH v1 2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table

[Jon Hunter]

On 30/08/2018 20:20, Dmitry Osipenko wrote:
> Add more predefined rates to the PLLX table, allowing to lower the rate
> down to 312MHz. This gives more variations of frequency selection to the
> CPUFREQ driver.

If these tables are pulled from some other NVIDIA kernel or a particular
document, I always like to see a reference to where these came from so
we can always refer back to them.

Cheers
Jon

-- 
nvpublic

Re: [PATCH v1 2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table

[Dmitry Osipenko]

On 10/17/18 11:59 AM, Jon Hunter wrote:
> 
> On 30/08/2018 20:20, Dmitry Osipenko wrote:
>> Add more predefined rates to the PLLX table, allowing to lower the rate
>> down to 312MHz. This gives more variations of frequency selection to the
>> CPUFREQ driver.
> 
> If these tables are pulled from some other NVIDIA kernel or a particular
> document, I always like to see a reference to where these came from so
> we can always refer back to them.

They are duplicates of T20 tables. But now this patch isn't actual and should be dropped because we will use other tables in the next iteration of the CPUFreq driver. Other patches still should be actual.

[PATCH v1 3/3] clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30

[Dmitry Osipenko]

Poll PLLX lock-status instead of delaying for a constant time. This speeds
up resume from suspend a tad and is less error-prone since lock failure
will be reported.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/clk/tegra/clk-tegra20.c | 51 +++++++++++++++++++++++++++------
 drivers/clk/tegra/clk-tegra30.c | 51 +++++++++++++++++++++++++++------
 2 files changed, 86 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index f987ed361df6..c8146e65e7ad 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -15,6 +15,7 @@
  */
 
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/of.h>
@@ -1001,6 +1002,47 @@ static void tegra20_cpu_clock_suspend(void)
 				readl(clk_base + SUPER_CCLK_DIVIDER);
 }
 
+static void tegra20_cpu_clock_restore_pllx(void)
+{
+	u32 misc = readl_relaxed(clk_base + PLLX_MISC);
+	u32 base = readl_relaxed(clk_base + PLLX_BASE);
+	u32 misc_restore = tegra20_cpu_clk_sctx.pllx_misc;
+	u32 base_restore = tegra20_cpu_clk_sctx.pllx_base;
+	int err;
+
+	/* nothing to do if PLL configuration is unchanged */
+	if (misc == misc_restore && base == base_restore)
+		return;
+
+	/* otherwise restore configuration */
+	if (base_restore & BIT(30)) {
+		/* PLL shall be locked if we are going to (re)enable it */
+		misc_restore |= BIT(18);
+	}
+
+	/* disable PLL if it is enabled to re-apply configuration safely */
+	if (base & BIT(30)) {
+		writel_relaxed(base & ~BIT(30), clk_base + PLLX_BASE);
+		udelay(1);
+	}
+
+	/* restore the configuration */
+	writel_relaxed(misc_restore, clk_base + PLLX_MISC);
+	writel_relaxed(base_restore, clk_base + PLLX_BASE);
+
+	/* PLL is disabled now, nothing left to do */
+	if (!(base_restore & BIT(30)))
+		return;
+
+	/* otherwise start polling the PLL lock-status */
+	err = readl_relaxed_poll_timeout_atomic(clk_base + PLLX_BASE, base,
+						base & BIT(27), 1, 2000);
+	/* should not happen */
+	WARN_ONCE(err, "PLLX failed to lock: %d\n", err);
+	/* post-enable delay */
+	udelay(50);
+}
+
 static void tegra20_cpu_clock_resume(void)
 {
 	unsigned int reg, policy;
@@ -1018,14 +1060,7 @@ static void tegra20_cpu_clock_resume(void)
 
 	if (reg != CCLK_BURST_POLICY_PLLX) {
 		/* restore PLLX settings if CPU is on different PLL */
-		writel(tegra20_cpu_clk_sctx.pllx_misc,
-					clk_base + PLLX_MISC);
-		writel(tegra20_cpu_clk_sctx.pllx_base,
-					clk_base + PLLX_BASE);
-
-		/* wait for PLL stabilization if PLLX was enabled */
-		if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
-			udelay(300);
+		tegra20_cpu_clock_restore_pllx();
 	}
 
 	/*
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0f8797ca39e2..0059fdf79169 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -15,6 +15,7 @@
  */
 
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
@@ -1189,6 +1190,47 @@ static void tegra30_cpu_clock_suspend(void)
 				readl(clk_base + CLK_RESET_CCLK_DIVIDER);
 }
 
+static void tegra30_cpu_clock_restore_pllx(void)
+{
+	u32 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
+	u32 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
+	u32 misc_restore = tegra30_cpu_clk_sctx.pllx_misc;
+	u32 base_restore = tegra30_cpu_clk_sctx.pllx_base;
+	int err;
+
+	/* nothing to do if PLL configuration is unchanged */
+	if (misc == misc_restore && base == base_restore)
+		return;
+
+	/* otherwise restore configuration */
+	if (base_restore & BIT(30)) {
+		/* PLL shall be locked if we are going to (re)enable it */
+		misc_restore |= BIT(18);
+	}
+
+	/* disable PLL if it is enabled to re-apply configuration safely */
+	if (base & BIT(30)) {
+		writel_relaxed(base & ~BIT(30), clk_base + CLK_RESET_PLLX_BASE);
+		udelay(1);
+	}
+
+	/* restore the configuration */
+	writel_relaxed(misc_restore, clk_base + CLK_RESET_PLLX_MISC);
+	writel_relaxed(base_restore, clk_base + CLK_RESET_PLLX_BASE);
+
+	/* PLL is disabled now, nothing left to do */
+	if (!(base_restore & BIT(30)))
+		return;
+
+	/* otherwise start polling the PLL lock-status */
+	err = readl_relaxed_poll_timeout_atomic(clk_base + CLK_RESET_PLLX_BASE,
+						base, base & BIT(27), 1, 2000);
+	/* should not happen */
+	WARN_ONCE(err, "PLLX failed to lock: %d\n", err);
+	/* post-enable delay */
+	udelay(50);
+}
+
 static void tegra30_cpu_clock_resume(void)
 {
 	unsigned int reg, policy;
@@ -1206,14 +1248,7 @@ static void tegra30_cpu_clock_resume(void)
 
 	if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
 		/* restore PLLX settings if CPU is on different PLL */
-		writel(tegra30_cpu_clk_sctx.pllx_misc,
-					clk_base + CLK_RESET_PLLX_MISC);
-		writel(tegra30_cpu_clk_sctx.pllx_base,
-					clk_base + CLK_RESET_PLLX_BASE);
-
-		/* wait for PLL stabilization if PLLX was enabled */
-		if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
-			udelay(300);
+		tegra30_cpu_clock_restore_pllx();
 	}
 
 	/*
-- 
2.18.0

Re: [PATCH v1 0/3] CPU clock changes for Tegra20/30

[Stephen Boyd]

Quoting Dmitry Osipenko (2018-08-30 12:20:42)
> Hello,
> 
> This series is a prerequisite for the CPUFREQ driver patches, it can be
> applied separately. CPUFREQ will be supported on Tegra30 once this and
> the CPUFREQ patch-series will be applied.
> 

Will anyone from Nvidia or Tegra review these patches? I'd rather not
apply something that has had zero review.