From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcel Ziswiler Subject: [PATCH v2 23/34] ARM: tegra: apalis_t30: enable emmc ddr52 mode Date: Fri, 31 Aug 2018 18:38:05 +0200 Message-ID: <20180831163817.23970-24-marcel@ziswiler.com> References: <20180831163817.23970-1-marcel@ziswiler.com> Return-path: In-Reply-To: <20180831163817.23970-1-marcel@ziswiler.com> Sender: linux-kernel-owner@vger.kernel.org To: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , Rob Herring , Mark Rutland List-Id: linux-tegra@vger.kernel.org From: Marcel Ziswiler Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@apalis-t30:~# cat /sys/kernel/debug/mmc1/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-t30:~# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 232 MB in 3.01 seconds = 77.10 MB/sec Signed-off-by: Marcel Ziswiler --- Changes in v2: None arch/arm/boot/dts/tegra30-apalis.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 2e2cdd454fe3..6d6f17422478 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1094,6 +1094,7 @@ non-removable; vmmc-supply = <®_module_3v3>; /* VCC */ vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; }; clocks { -- 2.14.4