From: Dmitry Osipenko <digetx@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] clk: tegra20: Enable lock-status polling for PLLs
Date: Tue, 4 Sep 2018 12:06:36 +0300 [thread overview]
Message-ID: <201809041206.37080.digetx@gmail.com> (raw)
In-Reply-To: <20180903080111.GR1636@tbergstrom-lnx.Nvidia.com>
On Monday 03 September 2018 11:01:11 Peter De Schrijver wrote:
> On Fri, Aug 31, 2018 at 12:45:17PM +0300, Dmitry Osipenko wrote:
> > On 8/31/18 12:29 PM, Peter De Schrijver wrote:
> > > On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
> > >> Currently all PLL's on Tegra20 use a hardcoded delay despite of having
> > >> a lock-status bit. The lock-status polling was disabled ~7 years ago
> > >> because PLLE was failing to lock and was a suspicion that other PLLs
> > >> might be faulty too. Other PLLs are okay, hence enable the lock-status
> > >> polling for them. This reduces delay of any operation that require PLL
> > >> to lock.
> > >>
> > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > >> ---
> > >>
> > >> Changelog:
> > >>
> > >> v2: Don't enable polling for PLLE as it known to not being able to
> > >> lock.
> > >
> > > This isn't correct. The lock bit of PLLE can declare lock too early,
> > > but the PLL itself does lock.
> >
> > Indeed, it locks but can't be polled for the lock-status as it doesn't
> > have the lock-status bit.
> >
> > Do you want me to adjust the commit description or it is fine as is?
>
> I think it's better to adjust it.
Okay. I expect to get a review from you for the other clock (and related)
patches too and will send the new version once all the current patches will
be reviewed. Please take a look at them once you'll have some free time,
thanks.
> > It is also a bit odd that PLLE has "lock_delay = 0", is it correct?
>
> That seems odd yes..
:)
next prev parent reply other threads:[~2018-09-04 9:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-30 18:42 [PATCH v2 1/2] clk: tegra: Don't enable already enabled PLLs Dmitry Osipenko
2018-08-30 18:42 ` [PATCH v2 2/2] clk: tegra20: Enable lock-status polling for PLLs Dmitry Osipenko
2018-08-31 9:29 ` Peter De Schrijver
2018-08-31 9:45 ` Dmitry Osipenko
2018-09-03 8:01 ` Peter De Schrijver
2018-09-04 9:06 ` Dmitry Osipenko [this message]
2018-10-17 11:52 ` Dmitry Osipenko
2018-10-17 10:59 ` Marcel Ziswiler
2018-10-17 11:41 ` Dmitry Osipenko
2018-12-10 0:58 ` Dmitry Osipenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=201809041206.37080.digetx@gmail.com \
--to=digetx@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=sboyd@kernel.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).