From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joseph Lo Subject: [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Date: Tue, 4 Dec 2018 17:25:47 +0800 Message-ID: <20181204092548.3038-19-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo List-Id: linux-tegra@vger.kernel.org Enable DFLL clock for Smaug board. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index b3930a9dd139..beac7b0bf436 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1698,6 +1698,18 @@ status = "okay"; }; + clock@70110000 { + status = "okay"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <&max77621_cpu>; + }; + aconnect@702c0000 { status = "okay"; -- 2.19.2