From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joseph Lo Subject: [PATCH V4 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Date: Fri, 4 Jan 2019 11:06:59 +0800 Message-ID: <20190104030702.8684-18-josephl@nvidia.com> References: <20190104030702.8684-1-josephl@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo List-Id: linux-tegra@vger.kernel.org Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V4: - s/nvidia,pwm-period/nvidia,pwm-period-nanoseconds/ *V3: - add ack tag *V2: - remove non exist DT bindings - update the PWM DT bindings accordingly --- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..9fad0d27278e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,25 @@ }; }; }; + + clock@70110000 { + status = "okay"; + + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,sample-rate = <25000>; + + nvidia,pwm-min-microvolts = <708000>; + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; }; -- 2.20.1