From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Jon Hunter <jonathanh@nvidia.com>
Subject: [PATCH 3/3] arm64: tegra: Fix base address for SOR1 on Tegra194
Date: Fri, 26 Jul 2019 12:16:18 +0200 [thread overview]
Message-ID: <20190726101618.26896-3-thierry.reding@gmail.com> (raw)
In-Reply-To: <20190726101618.26896-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 923415fd72a4..ca5ffbc79e2f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1045,7 +1045,7 @@
sor1: sor@15b40000 {
compatible = "nvidia,tegra194-sor";
- reg = <0x155c0000 0x40000>;
+ reg = <0x15b40000 0x40000>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
<&bpmp TEGRA194_CLK_SOR1_OUT>,
--
2.22.0
next prev parent reply other threads:[~2019-07-26 10:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 10:16 [PATCH 1/3] arm64: tegra: Add unit-address for CBB on Tegra194 Thierry Reding
2019-07-26 10:16 ` [PATCH 2/3] arm64: tegra: Add unit-address for ACONNECT " Thierry Reding
2019-07-26 10:16 ` Thierry Reding [this message]
2019-07-26 16:04 ` [PATCH 1/3] arm64: tegra: Add unit-address for CBB " mirq-test
2019-10-01 14:42 ` Thierry Reding
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