From: Thierry Reding <thierry.reding@gmail.com>
To: Ben Dooks <ben.dooks@codethink.co.uk>, Joerg Roedel <joro@8bytes.org>
Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org,
Ben Skeggs <bskeggs@redhat.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
Date: Mon, 16 Sep 2019 17:54:43 +0200 [thread overview]
Message-ID: <20190916155443.GF7488@ulmo> (raw)
In-Reply-To: <20190916154946.GD7488@ulmo>
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On Mon, Sep 16, 2019 at 05:49:46PM +0200, Thierry Reding wrote:
> On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote:
> > On 16/09/2019 16:04, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > There are extra registers that need to be programmed to make the level 2
> > > cache work on GP10B, such as the stream ID register that is used when an
> > > SMMU is used to translate memory addresses.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> > > .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 +
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++++++++++++++++++
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 +
> > > 5 files changed, 74 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > >
> > > diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > index 644d527c3b96..d76f60d7d29a 100644
> > > --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > #endif
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > index c3c7159f3411..d2d6d5f4028a 100644
> > > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > @@ -2380,7 +2380,7 @@ nv13b_chipset = {
> > > .fuse = gm107_fuse_new,
> > > .ibus = gp10b_ibus_new,
> > > .imem = gk20a_instmem_new,
> > > - .ltc = gp102_ltc_new,
> > > + .ltc = gp10b_ltc_new,
> > > .mc = gp10b_mc_new,
> > > .mmu = gp10b_mmu_new,
> > > .secboot = gp10b_secboot_new,
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > index 2b6d36ea7067..728d75010847 100644
> > > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > @@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o
> > > nvkm-y += nvkm/subdev/ltc/gm200.o
> > > nvkm-y += nvkm/subdev/ltc/gp100.o
> > > nvkm-y += nvkm/subdev/ltc/gp102.o
> > > +nvkm-y += nvkm/subdev/ltc/gp10b.o
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > > new file mode 100644
> > > index 000000000000..4d27c6ea1552
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > > @@ -0,0 +1,69 @@
> > > +/*
> > > + * Copyright (c) 2019 NVIDIA Corporation.
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > + * copy of this software and associated documentation files (the "Software"),
> > > + * to deal in the Software without restriction, including without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice shall be included in
> > > + * all copies or substantial portions of the Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > + * OTHER DEALINGS IN THE SOFTWARE.
> > > + *
> > > + * Authors: Thierry Reding
> > > + */
> > > +
> > > +#include "priv.h"
> > > +
> > > +static void
> > > +gp10b_ltc_init(struct nvkm_ltc *ltc)
> > > +{
> > > + struct nvkm_device *device = ltc->subdev.device;
> > > +#ifdef CONFIG_IOMMU_API
> > > + struct iommu_fwspec *spec;
> > > +#endif
> > > +
> > > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x100800, ltc->ltc_nr);
> > > +
> > > +#ifdef CONFIG_IOMMU_API
> > > + spec = dev_iommu_fwspec_get(device->dev);
> > > + if (spec) {
> > > + u32 sid = spec->ids[0] & 0xffff;
> > > +
> > > + /* stream ID */
> > > + nvkm_wr32(device, 0x160000, sid << 2);
> > > + }
> > > +#endif
> >
> > Could we get rid of the #ifdef blocks here if there was a NULL
> > inline version of dev_iommu_fwspec_get() in the include/linux/iommu.h
> > header? The compiler should then optimise the lot out if the config
> > is not set.
>
> I had thought the same thing and had even typed up the patch to add a
> dummy for dev_iommu_fwspec_get(), but then when I tested some builds, I
> got build errors nevertheless because struct iommu_fwspec is only
> declared under IOMMU_API.
>
> The obvious thing would have been to move struct iommu_fwspec outside of
> the IOMMU_API protection, but then I remembered having an earlier
> discussion with Joerg about something similar. I guess the issue here is
> that we need to reach into struct iommu_fwspec, so it has to be
> available in full.
>
> Anyway, I can add a patch to do this and remove the IOMMU_API guards,
> but let's see what Joerg thinks about that first.
>
> Joerg, to summarize: the proposal here is to move the declaration of the
> iommu_fwspec outside of the IOMMU_API guard and provide a dummy
> implementation of dev_iommu_fwspec_get() to allow this code to be built
> without the #ifdef guards. We had discussed something similar about 5
> years back and at the time you had been opposed:
>
> https://lore.kernel.org/linux-iommu/1406897113-20099-1-git-send-email-thierry.reding@gmail.com/
>
> The case here is slightly different and a lot of time has passed since,
> so just wanted to ask if your opinion here is the same, or whether you
> would accept a patch to make this buildable without resorting to
> #ifdef'ery.
>
> Thierry
Actually adding Joerg this time.
Thierry
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next prev parent reply other threads:[~2019-09-16 15:54 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-16 15:04 [PATCH 00/11] drm/nouveau: Enable GP10B by default Thierry Reding
[not found] ` <20190916150412.10025-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-09-16 15:04 ` [PATCH 01/11] drm/nouveau: tegra: Avoid pulsing reset twice Thierry Reding
2019-09-16 15:04 ` [PATCH 02/11] drm/nouveau: tegra: Set clock rate if not set Thierry Reding
2019-09-16 15:04 ` [PATCH 05/11] drm/nouveau: gp10b: Use correct copy engine Thierry Reding
2019-09-16 15:04 ` [PATCH 06/11] drm/nouveau: gk20a: Set IOMMU bit for DMA API if appropriate Thierry Reding
2019-09-16 15:04 ` [PATCH 07/11] drm/nouveau: gk20a: Implement custom MMU class Thierry Reding
2019-09-16 15:04 ` [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached Thierry Reding
2019-09-16 15:29 ` Robin Murphy
2019-09-16 15:57 ` Thierry Reding
2019-09-16 16:15 ` Robin Murphy
2019-09-17 7:59 ` Thierry Reding
2019-09-16 15:04 ` [PATCH 09/11] drm/nouveau: tegra: Fall back to 32-bit DMA mask without IOMMU Thierry Reding
2019-09-16 15:04 ` [PATCH 10/11] arm64: tegra: Enable GPU on Jetson TX2 Thierry Reding
2019-09-16 15:04 ` [PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers Thierry Reding
[not found] ` <20190916150412.10025-4-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-09-17 3:49 ` Ben Skeggs
[not found] ` <CACAvsv6AcwWW542AJNkyR-q+aQ0GLFc0C3Sior_bYPTEjBV4LA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-09-17 8:40 ` Thierry Reding
2019-09-17 23:28 ` Ben Skeggs
2019-09-16 15:04 ` [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation Thierry Reding
2019-09-16 15:35 ` Ben Dooks
2019-09-16 15:49 ` Thierry Reding
2019-09-16 15:54 ` Thierry Reding [this message]
2019-09-24 8:50 ` Joerg Roedel
2019-09-16 15:04 ` [PATCH 11/11] arm64: tegra: Enable SMMU for GPU on Tegra186 Thierry Reding
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