From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org, Sachin Nikam <snikam@nvidia.com>,
dri-devel@lists.freedesktop.org,
Puneet Saxena <puneets@nvidia.com>
Subject: [PATCH 10/12] drm/tegra: falcon: Clarify address usage
Date: Mon, 28 Oct 2019 13:37:16 +0100 [thread overview]
Message-ID: <20191028123718.3890217-11-thierry.reding@gmail.com> (raw)
In-Reply-To: <20191028123718.3890217-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Rename paddr -> iova and vaddr -> virt to make it clearer how these
addresses are used. This is important for a subsequent patch that makes
a distinction between the physical address (physical address of the
system memory from the CPU's point of view) and the IOVA (physical
address of the system memory from the device's point of view).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/drm/tegra/falcon.c | 14 ++++-----
drivers/gpu/drm/tegra/falcon.h | 5 +--
drivers/gpu/drm/tegra/vic.c | 56 +++++++++++++++-------------------
3 files changed, 34 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/tegra/falcon.c b/drivers/gpu/drm/tegra/falcon.c
index a5b25e4ecbd2..56edef06c48e 100644
--- a/drivers/gpu/drm/tegra/falcon.c
+++ b/drivers/gpu/drm/tegra/falcon.c
@@ -58,17 +58,17 @@ static int falcon_copy_chunk(struct falcon *falcon,
static void falcon_copy_firmware_image(struct falcon *falcon,
const struct firmware *firmware)
{
- u32 *firmware_vaddr = falcon->firmware.vaddr;
+ u32 *virt = falcon->firmware.virt;
size_t i;
/* copy the whole thing taking into account endianness */
for (i = 0; i < firmware->size / sizeof(u32); i++)
- firmware_vaddr[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
+ virt[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
}
static int falcon_parse_firmware_image(struct falcon *falcon)
{
- struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.vaddr;
+ struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.virt;
struct falcon_fw_os_header_v1 *os;
/* endian problems would show up right here */
@@ -89,7 +89,7 @@ static int falcon_parse_firmware_image(struct falcon *falcon)
return -EINVAL;
}
- os = falcon->firmware.vaddr + bin->os_header_offset;
+ os = falcon->firmware.virt + bin->os_header_offset;
falcon->firmware.bin_data.size = bin->os_size;
falcon->firmware.bin_data.offset = bin->os_data_offset;
@@ -138,7 +138,7 @@ int falcon_load_firmware(struct falcon *falcon)
int falcon_init(struct falcon *falcon)
{
- falcon->firmware.vaddr = NULL;
+ falcon->firmware.virt = NULL;
return 0;
}
@@ -155,7 +155,7 @@ int falcon_boot(struct falcon *falcon)
u32 value;
int err;
- if (!falcon->firmware.vaddr)
+ if (!falcon->firmware.virt)
return -EINVAL;
err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value,
@@ -168,7 +168,7 @@ int falcon_boot(struct falcon *falcon)
falcon_writel(falcon, 0, FALCON_DMACTL);
/* setup the address of the binary data so Falcon can access it later */
- falcon_writel(falcon, (falcon->firmware.paddr +
+ falcon_writel(falcon, (falcon->firmware.iova +
falcon->firmware.bin_data.offset) >> 8,
FALCON_DMATRFBASE);
diff --git a/drivers/gpu/drm/tegra/falcon.h b/drivers/gpu/drm/tegra/falcon.h
index 92491a1e90df..c56ee32d92ee 100644
--- a/drivers/gpu/drm/tegra/falcon.h
+++ b/drivers/gpu/drm/tegra/falcon.h
@@ -84,8 +84,9 @@ struct falcon_firmware {
const struct firmware *firmware;
/* Raw firmware data */
- dma_addr_t paddr;
- void *vaddr;
+ dma_addr_t iova;
+ dma_addr_t phys;
+ void *virt;
size_t size;
/* Parsed firmware information */
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index 4345b8054617..9444ba183990 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -133,9 +133,9 @@ static int vic_boot(struct vic *vic)
if (err < 0)
return err;
- hdr = vic->falcon.firmware.vaddr;
+ hdr = vic->falcon.firmware.virt;
fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
- hdr = vic->falcon.firmware.vaddr +
+ hdr = vic->falcon.firmware.virt +
*(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
@@ -143,7 +143,7 @@ static int vic_boot(struct vic *vic)
falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
fce_ucode_size);
falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
- (vic->falcon.firmware.paddr + fce_bin_data_offset)
+ (vic->falcon.firmware.iova + fce_bin_data_offset)
>> 8);
err = falcon_wait_idle(&vic->falcon);
@@ -225,14 +225,17 @@ static int vic_exit(struct host1x_client *client)
host1x_channel_put(vic->channel);
host1x_client_iommu_detach(client);
- if (client->group)
+ if (client->group) {
+ dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
+ vic->falcon.firmware.size, DMA_TO_DEVICE);
tegra_drm_free(tegra, vic->falcon.firmware.size,
- vic->falcon.firmware.vaddr,
- vic->falcon.firmware.paddr);
- else
+ vic->falcon.firmware.virt,
+ vic->falcon.firmware.iova);
+ } else {
dma_free_coherent(vic->dev, vic->falcon.firmware.size,
- vic->falcon.firmware.vaddr,
- vic->falcon.firmware.paddr);
+ vic->falcon.firmware.virt,
+ vic->falcon.firmware.iova);
+ }
return 0;
}
@@ -246,12 +249,12 @@ static int vic_load_firmware(struct vic *vic)
{
struct host1x_client *client = &vic->client.base;
struct tegra_drm *tegra = vic->client.drm;
- dma_addr_t phys;
+ dma_addr_t iova;
size_t size;
void *virt;
int err;
- if (vic->falcon.firmware.vaddr)
+ if (vic->falcon.firmware.virt)
return 0;
err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
@@ -261,17 +264,17 @@ static int vic_load_firmware(struct vic *vic)
size = vic->falcon.firmware.size;
if (!client->group) {
- virt = dma_alloc_coherent(vic->dev, size, &phys, GFP_KERNEL);
+ virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
- err = dma_mapping_error(vic->dev, phys);
+ err = dma_mapping_error(vic->dev, iova);
if (err < 0)
return err;
} else {
- virt = tegra_drm_alloc(tegra, size, &phys);
+ virt = tegra_drm_alloc(tegra, size, &iova);
}
- vic->falcon.firmware.vaddr = virt;
- vic->falcon.firmware.paddr = phys;
+ vic->falcon.firmware.virt = virt;
+ vic->falcon.firmware.iova = iova;
err = falcon_load_firmware(&vic->falcon);
if (err < 0)
@@ -283,35 +286,24 @@ static int vic_load_firmware(struct vic *vic)
* knows what memory pages to flush the cache for.
*/
if (client->group) {
+ dma_addr_t phys;
+
phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
err = dma_mapping_error(vic->dev, phys);
if (err < 0)
goto cleanup;
- /*
- * If the DMA API mapped this through a bounce buffer, the
- * dma_sync_single_for_device() call below will not be able
- * to flush the caches for the right memory pages. Output a
- * big warning in that case so that the DMA mask can be set
- * properly and the bounce buffer avoided.
- */
- WARN(phys != vic->falcon.firmware.paddr,
- "check DMA mask setting for %s\n", dev_name(vic->dev));
+ vic->falcon.firmware.phys = phys;
}
- dma_sync_single_for_device(vic->dev, phys, size, DMA_TO_DEVICE);
-
- if (client->group)
- dma_unmap_single(vic->dev, phys, size, DMA_TO_DEVICE);
-
return 0;
cleanup:
if (!client->group)
- dma_free_coherent(vic->dev, size, virt, phys);
+ dma_free_coherent(vic->dev, size, virt, iova);
else
- tegra_drm_free(tegra, size, virt, phys);
+ tegra_drm_free(tegra, size, virt, iova);
return err;
}
--
2.23.0
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next prev parent reply other threads:[~2019-10-28 12:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 12:37 [PATCH 00/12] drm/tegra: Support IOMMU-backed DMA API Thierry Reding
2019-10-28 12:37 ` [PATCH 01/12] memory: tegra: Add gr2d and gr3d to DRM IOMMU group Thierry Reding
2019-10-30 15:05 ` Dmitry Osipenko
2019-11-01 9:56 ` Thierry Reding
2019-10-28 12:37 ` [PATCH 02/12] drm/tegra: Simplify IOMMU group selection Thierry Reding
2019-10-28 12:37 ` [PATCH 03/12] gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API Thierry Reding
2019-10-28 12:37 ` [PATCH 04/12] gpu: host1x: Clean up debugfs on removal Thierry Reding
2019-10-28 12:37 ` [PATCH 05/12] gpu: host1x: Add direction flags to relocations Thierry Reding
2019-10-28 12:37 ` [PATCH 06/12] gpu: host1x: Allocate gather copy for host1x Thierry Reding
2019-10-28 12:37 ` [PATCH 07/12] gpu: host1x: Support DMA mapping of buffers Thierry Reding
2019-10-28 12:37 ` [PATCH 08/12] gpu: host1x: Set DMA mask based on IOMMU setup Thierry Reding
2019-10-28 12:37 ` [PATCH 09/12] drm/tegra: Remove memory allocation from Falcon library Thierry Reding
2019-10-28 12:37 ` Thierry Reding [this message]
2019-10-28 12:37 ` [PATCH 11/12] drm/tegra: Support DMA API for display controllers Thierry Reding
2019-10-28 12:37 ` [PATCH 12/12] drm/tegra: Optionally attach clients to the IOMMU Thierry Reding
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