From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding@gmail.com>
Subject: Re: [PATCH v1 11/29] ARM: tegra: Add interconnect properties to
 Tegra124 device-tree
Date: Tue, 19 Nov 2019 07:27:15 +0100
Message-ID: <20191119062715.GD2462695@ulmo>
References: <20191118200247.3567-1-digetx@gmail.com>
 <20191118200247.3567-12-digetx@gmail.com>
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To: Dmitry Osipenko <digetx@gmail.com>
Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Peter De Schrijver <pdeschrijver@nvidia.com>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Mikko Perttunen <mperttunen@nvidia.com>, Rob Herring <robh+dt@kernel.org>, linux-tegra@vger.kernel.org, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>
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On Mon, Nov 18, 2019 at 11:02:29PM +0300, Dmitry Osipenko wrote:
> Add interconnect properties to the memory controller, external memory
> controller and the display controller nodes to describe interconnection
> of these nodes.
>=20
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124=
=2Edtsi
> index 413bfb981de8..5069af3011cc 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -3,6 +3,7 @@
>  #include <dt-bindings/gpio/tegra-gpio.h>
>  #include <dt-bindings/memory/tegra124-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> +#include <dt-bindings/interconnect/tegra-icc.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/tegra124-car.h>
>  #include <dt-bindings/thermal/tegra124-soctherm.h>
> @@ -111,6 +112,9 @@
>  			iommus =3D <&mc TEGRA_SWGROUP_DC>;
> =20
>  			nvidia,head =3D <0>;
> +
> +			interconnects =3D <&mc TEGRA_ICC_MC_DC &emc TEGRA_ICC_EMEM>;
> +			interconnect-names =3D "dma-mem";

I don't think this is quite correct. The display controller is not
connected to the EMC. Instead, requests go to the MC which then forwards
them to the EMC. So I think we really only need the one connection here.
There are some clients that are read/write and they may need extra
entries, but all connections from memory clients should be to the MC,
not the EMC.

Thierry

>  		};
> =20
>  		dc@54240000 {
> @@ -126,6 +130,9 @@
>  			iommus =3D <&mc TEGRA_SWGROUP_DCB>;
> =20
>  			nvidia,head =3D <1>;
> +
> +			interconnects =3D <&mc TEGRA_ICC_MC_DCB &emc TEGRA_ICC_EMEM>;
> +			interconnect-names =3D "dma-mem";
>  		};
> =20
>  		hdmi: hdmi@54280000 {
> @@ -620,6 +627,7 @@
>  		interrupts =3D <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> =20
>  		#iommu-cells =3D <1>;
> +		#interconnect-cells =3D <1>;
>  	};
> =20
>  	emc: emc@7001b000 {
> @@ -627,6 +635,8 @@
>  		reg =3D <0x0 0x7001b000 0x0 0x1000>;
> =20
>  		nvidia,memory-controller =3D <&mc>;
> +
> +		#interconnect-cells =3D <1>;
>  	};
> =20
>  	sata@70020000 {
> --=20
> 2.23.0
>=20

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