From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v1] ARM: dts: tegra20: paz00: Add memory timings
Date: Fri, 10 Jan 2020 15:42:31 +0100
Message-ID: <20200110144231.GF2233456@ulmo>
References: <20191218185957.29237-1-digetx@gmail.com>
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To: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>, Nicolas Chauvet <kwizart-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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On Wed, Dec 18, 2019 at 09:59:57PM +0300, Dmitry Osipenko wrote:
> PAZ00 board has two variants of DDR2 SDRAM devices for External Memory:
> one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H.
> The Micron variant doesn't have official timings in the wild, hence only
> timings for the Hynix are added. The memory frequency-scaling was tested
> using the Tegra20 devfreq driver.
>=20
> Tested-by: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra20-paz00.dts | 46 +++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)

Applied to for-5.6/arm/dt, thanks.

Thierry

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