From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Wed, 05 Feb 2020 11:23:41 -0800 Message-ID: <20200205192341.E4E482072B@mail.kernel.org> References: <1580235801-4129-1-git-send-email-skomatineni@nvidia.com> <1580235801-4129-3-git-send-email-skomatineni@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1580235801-4129-3-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: frankc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org, jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org Quoting Sowjanya Komatineni (2020-01-28 10:23:18) > Tegra210 CSI hardware internally uses PLLD for internal test pattern > generator logic. >=20 > PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD > out to CSI during TPG mode. >=20 > This patch adds this CSI TPG clock gate to Tegra210 clock driver > to allow Tegra video driver to ungate CSI TPG clock during TPG mode > and gate during non TPG mode. >=20 > Signed-off-by: Sowjanya Komatineni > --- Acked-by: Stephen Boyd