From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: [PATCH 02/38] dt-bindings: memory: nvidia: Mark memory controller as interconnect provider Date: Fri, 12 Jun 2020 16:18:27 +0200 Message-ID: <20200612141903.2391044-3-thierry.reding@gmail.com> References: <20200612141903.2391044-1-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org From: Thierry Reding Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra186-mc.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 611bda38d187..581572fe3077 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -38,6 +38,16 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 1 + description: + Each interconnect node for the memory controller takes a phandle to the + memory controller and a single cell as the specifier, identifying the + memory client by its ID. + + For a list of valid IDs, see dt-bindings/memory/tegra186-mc.h and + dt-bindings/memory/tegra194-mc.h. + "#address-cells": const: 2 -- 2.24.1