From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: [PATCH 29/38] dt-bindings: tegra: pmc: Increase clock limit for power domains Date: Fri, 12 Jun 2020 16:18:54 +0200 Message-ID: <20200612141903.2391044-30-thierry.reding@gmail.com> References: <20200612141903.2391044-1-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200612141903.2391044-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org From: Thierry Reding Power domains (such as the SOR domain) can have more than 8 clocks. Bump the limit to 10 which is enough as of now. Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 81534d04094b..881bfc6154e2 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -213,7 +213,7 @@ properties: patternProperties: clocks: minItems: 1 - maxItems: 8 + maxItems: 10 description: Must contain an entry for each clock required by the PMC for controlling a power-gate. -- 2.24.1