From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH 2/3] arm64: tegra: Enable DFLL support on Jetson Nano
Date: Tue, 14 Jul 2020 11:18:49 +0200
Message-ID: <20200714091849.GD141356@ulmo>
References: <20200712102506.23686-1-jonathanh@nvidia.com>
 <20200712102506.23686-3-jonathanh@nvidia.com>
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To: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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On Sun, Jul 12, 2020 at 11:25:05AM +0100, Jon Hunter wrote:
> Populate the DFLL node and corresponding PWM pin nodes in order to
> enable CPUFREQ support on the Jetson Nano platform.
>=20
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../boot/dts/nvidia/tegra210-p3450-0000.dts   | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)

Applied, thanks.

Thierry

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