From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: [PATCH v3 2/2] arm64: tegra: Add the GPU on Tegra194 Date: Fri, 17 Jul 2020 10:36:09 +0200 Message-ID: <20200717083609.557205-2-thierry.reding@gmail.com> References: <20200717083609.557205-1-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200717083609.557205-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Rob Herring , Jon Hunter , Terje Bergstrom , Debarshi Dutta , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-tegra@vger.kernel.org From: Thierry Reding The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called GV11B. Signed-off-by: Thierry Reding --- Changes in v3: - mark the GPU as DMA coherent because that's enforced by the MSS - add FUSE clock which is needed during GPU initialization - enable GPU by default arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 98c366ab4aab..48160f48003a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1395,6 +1395,40 @@ sor3: sor@15bc0000 { nvidia,interface = <3>; }; }; + + gpu@17000000 { + compatible = "nvidia,gv11b"; + reg = <0x17000000 0x10000000>, + <0x18000000 0x10000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + clocks = <&bpmp TEGRA194_CLK_GPCCLK>, + <&bpmp TEGRA194_CLK_GPU_PWR>, + <&bpmp TEGRA194_CLK_FUSE>; + clock-names = "gpu", "pwr", "fuse"; + resets = <&bpmp TEGRA194_RESET_GPU>; + reset-names = "gpu"; + dma-coherent; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; + interconnect-names = "dma-mem", "read-0-hp", "write-0", + "read-1", "read-1-hp", "write-1", + "read-2", "read-2-hp", "write-2", + "read-3", "read-3-hp", "write-3"; + }; }; pcie@14100000 { -- 2.27.0