From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: Wright Feng <Wright.Feng@cypress.com>, linux-tegra@vger.kernel.org
Subject: [PATCH v1 2/4] ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50MHz
Date: Sun, 23 Aug 2020 17:47:23 +0300 [thread overview]
Message-ID: <20200823144725.28299-3-digetx@gmail.com> (raw)
In-Reply-To: <20200823144725.28299-1-digetx@gmail.com>
Previously 50MHz clock rate didn't work because of the wrong PINCTRL
configuration used for SDIO pins. Now the PINCTRL config is corrected
and the MMC clock rate could be bumped safely to 50MHz, increasing WiFi
TX throughput by 20 Mbit/s and allowing to hit the maximum 40 Mbit/s.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index 8b4912db0d20..b89e9398f681 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -744,7 +744,7 @@ mmc@c8000000 {
#address-cells = <1>;
#size-cells = <0>;
- max-frequency = <25000000>;
+ max-frequency = <50000000>;
keep-power-in-suspend;
bus-width = <4>;
non-removable;
--
2.27.0
next prev parent reply other threads:[~2020-08-23 14:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-23 14:47 [PATCH v1 0/4] WiFi SDIO fixes and improvements for Acer A500 and Nexus 7 Dmitry Osipenko
2020-08-23 14:47 ` [PATCH v1 1/4] ARM: tegra: acer-a500: Correct PINCTRL configuration Dmitry Osipenko
2020-08-23 14:47 ` Dmitry Osipenko [this message]
2020-08-23 14:47 ` [PATCH v1 3/4] ARM: tegra: acer-a500: Use PLLC for WiFi MMC clk parent Dmitry Osipenko
2020-08-23 14:47 ` [PATCH v1 4/4] ARM: tegra: nexus7: " Dmitry Osipenko
2020-09-17 10:21 ` [PATCH v1 0/4] WiFi SDIO fixes and improvements for Acer A500 and Nexus 7 Thierry Reding
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