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Mon, 14 Sep 2020 14:18:04 +0000 Received: from pps.filterd (aserp3030.oracle.com [127.0.0.1]) by aserp3030.oracle.com (8.16.0.42/8.16.0.42) with SMTP id 08EEFvOe011616; Mon, 14 Sep 2020 14:18:04 GMT Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserp3030.oracle.com with ESMTP id 33h7wm80qk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 14 Sep 2020 14:18:04 +0000 Received: from abhmp0005.oracle.com (abhmp0005.oracle.com [141.146.116.11]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 08EEI2tm001838; Mon, 14 Sep 2020 14:18:02 GMT Received: from kadam (/41.57.98.10) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 14 Sep 2020 14:18:01 +0000 Date: Mon, 14 Sep 2020 17:17:54 +0300 From: Dan Carpenter To: Dmitry Osipenko Cc: Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Thierry Reding , Jonathan Hunter , linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH] PM / devfreq: tegra30: disable clock on error in probe Message-ID: <20200914141754.GB18329@kadam> References: <20200908072557.GC294938@mwanda> <2ceb045a-ebac-58d7-0250-4ea39d711ce8@samsung.com> <44560522-f04e-ade5-2e02-9df56a6f79ba@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <44560522-f04e-ade5-2e02-9df56a6f79ba@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9744 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009140117 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9743 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009140117 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Mon, Sep 14, 2020 at 04:56:26PM +0300, Dmitry Osipenko wrote: > 14.09.2020 10:09, Chanwoo Choi пишет: > > Hi, > > > > On 9/8/20 4:25 PM, Dan Carpenter wrote: > >> This error path needs to call clk_disable_unprepare(). > >> > >> Fixes: 7296443b900e ("PM / devfreq: tegra30: Handle possible round-rate error") > >> Signed-off-by: Dan Carpenter > >> --- > >> --- > >> drivers/devfreq/tegra30-devfreq.c | 4 +++- > >> 1 file changed, 3 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c > >> index e94a27804c20..dedd39de7367 100644 > >> --- a/drivers/devfreq/tegra30-devfreq.c > >> +++ b/drivers/devfreq/tegra30-devfreq.c > >> @@ -836,7 +836,8 @@ static int tegra_devfreq_probe(struct platform_device *pdev) > >> rate = clk_round_rate(tegra->emc_clock, ULONG_MAX); > >> if (rate < 0) { > >> dev_err(&pdev->dev, "Failed to round clock rate: %ld\n", rate); > >> - return rate; > >> + err = rate; > >> + goto disable_clk; > >> } > >> > >> tegra->max_freq = rate / KHZ; > >> @@ -897,6 +898,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev) > >> dev_pm_opp_remove_all_dynamic(&pdev->dev); > >> > >> reset_control_reset(tegra->reset); > >> +disable_clk: > >> clk_disable_unprepare(tegra->clock); > > > > Is it doesn't need to reset with reset_contrl_reset()? > > Hello, Chanwoo! > > It's reset just before the clk_round_rate() invocation, hence there > shouldn't be a need to reset it second time. Ah... I was looking the wrong code. Plus I don't really know this code very well. If clk_prepare_enable() fails, then I would have assumed we need to call reset_control_deassert(). I would have assumed the reset_control_assert() and _deassert() functions were paired. So what I'm suggesting is something like the following: (I'll resend this if it's correct). [PATCH] PM / devfreq: tegra30: Add missing reset_control_deassert() If clk_prepare_enable() fails then probe needs to call the reset_control_deassert() function. Fixes: 6234f38016ad ("PM / devfreq: tegra: add devfreq driver for Tegra Activity Monitor") Signed-off-by: Dan Carpenter --- drivers/devfreq/tegra30-devfreq.c | 1 + 1 file changed, 1 insertions(+), 0 deletion(-) diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index e94a27804c20..ce217aba7b9d 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -828,6 +828,7 @@ static int tegra_devfreq_probe(struct platform_device *pdev) if (err) { dev_err(&pdev->dev, "Failed to prepare and enable ACTMON clock\n"); + reset_control_deassert(tegra->reset); return err; }