From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67BADC388F7 for ; Wed, 28 Oct 2020 22:12:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1806024724 for ; Wed, 28 Oct 2020 22:12:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603923129; bh=oTW2qxr417IFrYMw5d19YWxMQQBH3NrvvNvpAFXxV7s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=VVv0sGon3YaLmzsksMFc/UJ0RaKXDkTDy4bv9YGYlQfb90ZTlFERg3cBzzxhQdxe2 Cli7zLi3tLppGDT1qdGE2iNAtCWbNVFhG7erfdLt3YVq2ELV0THYfbydd6UhIXIHgF 2731XGVjxt65kW+Tbeuh+F5MOlWLZqhkerQ7DaxM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730767AbgJ1WL4 (ORCPT ); Wed, 28 Oct 2020 18:11:56 -0400 Received: from mail-yb1-f195.google.com ([209.85.219.195]:35661 "EHLO mail-yb1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730760AbgJ1WLz (ORCPT ); Wed, 28 Oct 2020 18:11:55 -0400 Received: by mail-yb1-f195.google.com with SMTP id m188so504089ybf.2; Wed, 28 Oct 2020 15:11:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=T8MLPXzg2SZx9c5xJhUu8LnS9OjmrbIOKKCNscuh58o=; b=HOXi0BWmmQuKMoTzj0yDIlJF6ZWhxNG4O12J5pdvyoobkGFfTWm8mvkPSs72NN53nD MU6xAziewhZwQX682lWYaD7umS/oshawRcoeGVCE2jSUiASeL9dHN6CdYEDo82Hezxu2 BwbvabQo8cERzT8xiA37gq1DKp1iz6GB8zy+I/mCZpgeeNEXtd36Ic1UoKPz9tpiMA1R ibarWJaZUT7vysKoW6zDIFpZ6nEZZ95yd4M6hqqXWNv5H1VefXQQP7dUkrPRHXzrJwNJ hGFp+LiUhmrUgKsHiQh6qYTQxRt+JxPRlwzoP2oDLvxlCcPjIC52x97mLn4nEeF+40Vi 2cvQ== X-Gm-Message-State: AOAM5327QgqUKDQ9ITSWjmo3N0yLNydIxxYgUZKehtLe45oKGfCeG0AM OOFW3w3YNNck6T4GcmVUGdUFxR3GGw== X-Google-Smtp-Source: ABdhPJz7reJgOyNPbR/RoD8e8RtXXbZyuobF3ZC3HQeIbo0bO8WjCWxfxCDoSnL/csJ+nowSt3xcZA== X-Received: by 2002:a9d:6307:: with SMTP id q7mr5698617otk.218.1603898611758; Wed, 28 Oct 2020 08:23:31 -0700 (PDT) Received: from xps15 (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id f18sm2703272oos.19.2020.10.28.08.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2020 08:23:31 -0700 (PDT) Received: (nullmailer pid 4050728 invoked by uid 1000); Wed, 28 Oct 2020 15:23:29 -0000 Date: Wed, 28 Oct 2020 10:23:29 -0500 From: Rob Herring To: Dmitry Osipenko Cc: Stephen Boyd , linux-pm@vger.kernel.org, Georgi Djakov , Peter De Schrijver , Peter Geis , Jonathan Hunter , Rob Herring , Kyungmin Park , Nicolas Chauvet , Krzysztof Kozlowski , devicetree@vger.kernel.org, Chanwoo Choi , Thierry Reding , Michael Turquette , Mikko Perttunen , MyungJoo Ham , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Viresh Kumar Subject: Re: [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Message-ID: <20201028152329.GA4050679@bogus> References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-5-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201025221735.3062-5-digetx@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Mon, 26 Oct 2020 01:16:47 +0300, Dmitry Osipenko wrote: > Tegra20 External Memory Controller talks to DRAM chips and it needs to be > reprogrammed when memory frequency changes. Tegra Memory Controller sits > behind EMC and these controllers are tightly coupled. This patch adds the > new phandle property which allows to properly express connection of EMC > and MC hardware in a device-tree, it also put the Tegra20 EMC binding on > par with Tegra30+ EMC bindings, which is handy to have. > > Signed-off-by: Dmitry Osipenko > --- > .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring