From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
Nicolin Chen <nicolinc@nvidia.com>,
Krishna Reddy <vdumpa@nvidia.com>,
linux-tegra@vger.kernel.org, iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/9] memory: tegra: Implement SID override programming
Date: Thu, 25 Mar 2021 14:03:26 +0100 [thread overview]
Message-ID: <20210325130332.778208-4-thierry.reding@gmail.com> (raw)
In-Reply-To: <20210325130332.778208-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Instead of programming all SID overrides during early boot, perform the
operation on-demand after the SMMU translations have been set up for a
device. This reuses data from device tree to match memory clients for a
device and programs the SID specified in device tree, which corresponds
to the SID used for the SMMU context banks for the device.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/memory/tegra/tegra186.c | 70 +++++++++++++++++++++++++++++++++
include/soc/tegra/mc.h | 10 +++++
2 files changed, 80 insertions(+)
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index efa922d51d83..a89e8e40d875 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -4,6 +4,7 @@
*/
#include <linux/io.h>
+#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
@@ -19,6 +20,10 @@
#include <dt-bindings/memory/tegra194-mc.h>
#endif
+#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
+#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
+#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
+
struct tegra186_mc_client {
const char *name;
unsigned int id;
@@ -1808,6 +1813,71 @@ static struct platform_driver tegra186_mc_driver = {
};
module_platform_driver(tegra186_mc_driver);
+static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
+ const struct tegra186_mc_client *client,
+ unsigned int sid)
+{
+ u32 value, old;
+
+ value = readl(mc->regs + client->regs.security);
+ if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
+ /*
+ * If the secure firmware has locked this down the override
+ * for this memory client, there's nothing we can do here.
+ */
+ if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
+ return;
+
+ /*
+ * Otherwise, try to set the override itself. Typically the
+ * secure firmware will never have set this configuration.
+ * Instead, it will either have disabled write access to
+ * this field, or it will already have set an explicit
+ * override itself.
+ */
+ WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
+
+ value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
+ writel(value, mc->regs + client->regs.security);
+ }
+
+ value = readl(mc->regs + client->regs.override);
+ old = value & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ if (old != sid) {
+ dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
+ client->name, sid);
+ writel(sid, mc->regs + client->regs.override);
+ }
+}
+
+int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct of_phandle_args args;
+ unsigned int i, index = 0;
+
+ while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
+ index, &args)) {
+ if (args.np == mc->dev->of_node && args.args_count != 0) {
+ for (i = 0; i < mc->soc->num_clients; i++) {
+ const struct tegra186_mc_client *client = &mc->soc->clients[i];
+
+ if (client->id == args.args[0]) {
+ u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ tegra186_mc_client_sid_override(mc, client, sid);
+ }
+ }
+ }
+
+ index++;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra186_mc_probe_device);
+
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver");
MODULE_LICENSE("GPL v2");
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 7be8441c6e9e..73d5ecf0e76a 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -168,4 +168,14 @@ devm_tegra_memory_controller_get(struct device *dev)
}
#endif
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
+ IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
+int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev);
+#else
+static inline int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+ return 0;
+}
+#endif
+
#endif /* __SOC_TEGRA_MC_H__ */
--
2.30.2
next prev parent reply other threads:[~2021-03-25 13:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 13:03 [PATCH 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
2021-03-25 13:03 ` [PATCH 1/9] memory: tegra: Move internal data structures into separate header Thierry Reding
2021-03-25 15:12 ` Dmitry Osipenko
2021-03-25 15:52 ` Thierry Reding
2021-03-25 16:11 ` Dmitry Osipenko
2021-03-26 13:21 ` Dmitry Osipenko
2021-03-25 13:03 ` [PATCH 2/9] memory: tegra: Add memory client IDs to tables Thierry Reding
2021-03-25 13:03 ` Thierry Reding [this message]
2021-03-25 14:27 ` [PATCH 3/9] memory: tegra: Implement SID override programming Robin Murphy
2021-03-25 15:02 ` Thierry Reding
2021-03-25 13:03 ` [PATCH 4/9] iommu/arm-smmu: Implement ->probe_finalize() Thierry Reding
2021-03-25 14:27 ` Robin Murphy
2021-03-25 13:03 ` [PATCH 5/9] iommu/arm-smmu: tegra: Detect number of instances at runtime Thierry Reding
2021-03-25 14:27 ` Robin Murphy
2021-03-25 13:03 ` [PATCH 6/9] iommu/arm-smmu: tegra: Implement SID override programming Thierry Reding
2021-03-25 13:03 ` [PATCH 7/9] iommu/arm-smmu: Use Tegra implementation on Tegra186 Thierry Reding
2021-03-25 14:27 ` Robin Murphy
2021-03-25 13:03 ` [PATCH 8/9] arm64: tegra: Hook up memory controller to SMMU " Thierry Reding
2021-03-25 13:03 ` [PATCH 9/9] arm64: tegra: Enable SMMU support on Tegra194 Thierry Reding
2021-03-26 15:29 ` [PATCH 0/9] arm64: tegra: Prevent early SMMU faults Dmitry Osipenko
2021-03-26 16:35 ` Thierry Reding
2021-03-26 16:55 ` Dmitry Osipenko
2021-03-26 22:05 ` Dmitry Osipenko
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