From: Nicolin Chen <nicolinc@nvidia.com>
To: <joro@8bytes.org>, <will@kernel.org>, <robin.murphy@arm.com>
Cc: <nicoleotsuka@gmail.com>, <thierry.reding@gmail.com>,
<vdumpa@nvidia.com>, <nwatterson@nvidia.com>,
<jean-philippe@linaro.org>, <thunder.leizhen@huawei.com>,
<chenxiang66@hisilicon.com>, <Jonathan.Cameron@huawei.com>,
<yuzenghui@huawei.com>, <linux-kernel@vger.kernel.org>,
<iommu@lists.linux-foundation.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <jgg@nvidia.com>
Subject: [PATCH v3 1/5] iommu/arm-smmu-v3: Add CS_NONE quirk
Date: Thu, 18 Nov 2021 23:19:55 -0800 [thread overview]
Message-ID: <20211119071959.16706-2-nicolinc@nvidia.com> (raw)
In-Reply-To: <20211119071959.16706-1-nicolinc@nvidia.com>
The CMDQV extension in NVIDIA Grace SoC only supports CS_NONE in the
CS field of CMD_SYNC. So this patch adds a quirk flag to accommodate
that.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 ++++++-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index f5848b351b19..e6fee69dd79c 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -319,7 +319,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag);
break;
case CMDQ_OP_CMD_SYNC:
- if (ent->sync.msiaddr) {
+ if (ent->sync.cs_none) {
+ cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE);
+ } else if (ent->sync.msiaddr) {
cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);
cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK;
} else {
@@ -356,6 +358,9 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,
q->ent_dwords * 8;
}
+ if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)
+ ent.sync.cs_none = true;
+
arm_smmu_cmdq_build_cmd(cmd, &ent);
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 4cb136f07914..7a6a6045700d 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -499,6 +499,7 @@ struct arm_smmu_cmdq_ent {
#define CMDQ_OP_CMD_SYNC 0x46
struct {
u64 msiaddr;
+ bool cs_none;
} sync;
};
};
@@ -531,6 +532,9 @@ struct arm_smmu_queue {
u32 __iomem *prod_reg;
u32 __iomem *cons_reg;
+
+#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */
+ u32 quirks;
};
struct arm_smmu_queue_poll {
--
2.17.1
next prev parent reply other threads:[~2021-11-19 7:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 7:19 [PATCH v3 0/5] iommu/arm-smmu-v3: Add NVIDIA Grace CMDQ-V Support Nicolin Chen
2021-11-19 7:19 ` Nicolin Chen [this message]
2021-11-19 7:19 ` [PATCH v3 2/5] iommu/arm-smmu-v3: Make arm_smmu_cmdq_init reusable Nicolin Chen
2021-11-19 7:19 ` [PATCH v3 3/5] iommu/arm-smmu-v3: Pass cmdq pointer in arm_smmu_cmdq_issue_cmdlist() Nicolin Chen
2021-11-19 7:19 ` [PATCH v3 4/5] iommu/arm-smmu-v3: Add host support for NVIDIA Grace CMDQ-V Nicolin Chen
2021-12-20 18:42 ` Robin Murphy
2021-12-20 19:27 ` Nicolin Chen
2021-12-21 18:55 ` Robin Murphy
2021-12-21 22:00 ` Nicolin Chen
2021-12-22 11:57 ` Robin Murphy
2021-11-19 7:19 ` [PATCH v3 5/5] iommu/nvidia-grace-cmdqv: Limit CMDs for guest owned VINTF Nicolin Chen
2021-12-22 12:32 ` Robin Murphy
2021-12-22 22:52 ` Nicolin Chen
2021-12-23 11:14 ` Robin Murphy
2021-12-24 8:02 ` Nicolin Chen
2021-12-24 12:13 ` Robin Murphy
2021-12-28 5:49 ` Nicolin Chen
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