From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44463C433F5 for ; Thu, 9 Dec 2021 16:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239459AbhLIQjt (ORCPT ); Thu, 9 Dec 2021 11:39:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239464AbhLIQjt (ORCPT ); Thu, 9 Dec 2021 11:39:49 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85435C061746; Thu, 9 Dec 2021 08:36:15 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id c4so10662945wrd.9; Thu, 09 Dec 2021 08:36:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cpB5QnL+Wf4tMDBJIxxBMIETOl3RQ/RiRgw6HjScLLM=; b=jzKaywGyMIKZ+3Ix9/pUnisQuJEIogyL7ecrGCELw7K2y1NE6vtVR5fP/ed4tWguRv Aw+Q3oQ2AUgSq9Mrz3Ov9AO5WXGYfT49bee2KZHV8CltZPCn2srMDCmqVO0wLHd4G5X6 3BDEYA2xh4jlBebbTZ+UBM9Lvp43YPhozpsaHMxcDBxu0dm1gp22k4sRCJ16fKnUgoAL 0zxOtFcLNOhnBepFcVsogKlSStmeNg3eFNDunJ6LcTBc4iFowTEnxsgEItBCUeJdeR4M 1qfdhulb32cLzWpwH2OvEI76HlHr+bvnepWbs382Fg9Ks1oKe115nJOhVSJxb/FAO/vj c09g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cpB5QnL+Wf4tMDBJIxxBMIETOl3RQ/RiRgw6HjScLLM=; b=d4mrMlTKHpJsAmIz7qPI78Iiz7hmcqO9GxDyd3KdANX6vWEU1DaUQwIBf/D5lwEuMN /pjhCwRvZxxjgJZ7ajwVw1p/nMKfmOaJgaSN/SF6YKHZ9W6AAgCIraRrX3BnRxil/115 3+p6UV1ky3Zri2bT2RBWYaGqZjGnONfsKj5KenkC5LAAAVXC+k2hpCxI1Si4ah3PQJ2D lMonHfpwMC1IDa8WDgSrDmY4+i2bixWQFOfpiUaK5myXKbtoW6zcycq7mojvprb6PipZ /EGhb9m5lTmWxhnhc+PbALxdZ121l29CeoHtuw8zo5ciu/bZVo5POGJt1puZHXvdBR3R nOZg== X-Gm-Message-State: AOAM532emP9Bp7iOVzeA3RElZnB3TaT/Sy0dm0+HFGYc0TDsy/lUvK+y EO/zvJi2OPlKGZYp16P3v64= X-Google-Smtp-Source: ABdhPJwPfh9nB8a6JAVGrI8XVNxvUGzdtAKyrwPeQ7A0IEowOB/7N1BpnlgCMyx7a2s7STz1WLrzUQ== X-Received: by 2002:a5d:5588:: with SMTP id i8mr7555511wrv.552.1639067774028; Thu, 09 Dec 2021 08:36:14 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l21sm175967wrb.38.2021.12.09.08.36.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 08:36:13 -0800 (PST) From: Thierry Reding To: Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring Cc: Thierry Reding , Jon Hunter , iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] arm64: tegra: Add Tegra234 IOMMUs Date: Thu, 9 Dec 2021 17:36:00 +0100 Message-Id: <20211209163600.609613-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209163600.609613-1-thierry.reding@gmail.com> References: <20211209163600.609613-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by isochronous memory clients and two dual-instance ARM SMMUs used by non- isochronous memory clients. Add the corresponding device tree nodes and hook up existing memory clients (SDHCI and BPMP). Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 426 +++++++++++++++++++++++ 1 file changed, 426 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 3df2217fd826..7acae44a09b8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -160,6 +160,7 @@ mmc@3460000 { interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -198,6 +199,148 @@ hsp_top0: hsp@3c00000 { #mbox-cells = <2>; }; + smmu_niso1: iommu@8000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x8000000 0x1000000>, + <0x7000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -262,6 +405,288 @@ gic: interrupt-controller@f400000 { #interrupt-cells = <3>; interrupt-controller; }; + + smmu_iso: iommu@10000000{ + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + + smmu_niso0: iommu@12000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x12000000 0x1000000>, + <0x11000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; }; sram@40000000 { @@ -297,6 +722,7 @@ bpmp: bpmp { <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; -- 2.34.1