[PATCH v3 1/6] dt-bindings: memory: tegra: Update for Tegra194

Thierry Reding
2021-12-13T16:22:00Z

The #interconnect-cells properties are required to hook up memory
clients to the MC/EMC in interconnects properties. Add a description for
these properties.

For the nested EMC controller, the list of required properties was
missing. Add it so that the validation can be more strict.

Also, allow multiple reg entries required by Tegra194 and later.

While at it, also remove the dummy BPMP node from the example because it
is incomplete and fails validation. It's also not necessary for this
file and the BPMP DT schema already has a full example.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- reword commit message to reflect changes in v2

Changes in v2:
- drop incomplete BPMP snippet from example
- explicitly set minItems for reg property
- describe MC and EMC general interrupts
- add required properties for EMC

.../nvidia,tegra186-mc.yaml | 78 ++++++++++++++++---
1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 611bda38d187..b496564b1bdf 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -33,10 +33,12 @@ properties:
- nvidia,tegra194-mc

reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 3

interrupts:
- maxItems: 1
+ items:
+ - description: MC general interrupt

"#address-cells":
const: 2
@@ -48,6 +50,9 @@ properties:

dma-ranges: true

+ "#interconnect-cells":
+ const: 1
+
patternProperties:
"^external-memory-controller@[0-9a-f]+$":
description:
@@ -65,10 +70,12 @@ patternProperties:
- nvidia,tegra194-emc

reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2

interrupts:
- maxItems: 1
+ items:
+ - description: EMC general interrupt

clocks:
items:
@@ -78,11 +85,65 @@ patternProperties:
items:
- const: emc

+ "#interconnect-cells":
+ const: 0
+
nvidia,bpmp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the node representing the BPMP

+ allOf:
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra186-emc
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra194-emc
+ then:
+ properties:
+ reg:
+ minItems: 2
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#interconnect-cells"
+ - nvidia,bpmp
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra186-mc
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra194-mc
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -90,8 +151,6 @@ required:
- "#address-cells"
- "#size-cells"

-additionalProperties: false
-
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
@@ -124,12 +183,9 @@ examples:
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";

+ #interconnect-cells = <0>;
+
nvidia,bpmp = <&bpmp>;
};
};
};
-
- bpmp: bpmp {
- compatible = "nvidia,tegra186-bpmp";
- #clock-cells = <1>;
- };
--
2.34.1