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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id ot7sm4268637pjb.12.2022.01.05.14.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 14:11:51 -0800 (PST) Date: Wed, 5 Jan 2022 14:11:50 -0800 From: Kees Cook To: Jani Nikula Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, Thierry Reding , Jonathan Hunter , Philipp Zabel , Lyude Paul , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-hardening@vger.kernel.org Subject: Re: [PATCH] drm/dp: Remove common Post Cursor2 register handling Message-ID: <202201051410.8F65E4E0@keescook> References: <20220105173507.2420910-1-keescook@chromium.org> <878rvujc4t.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <878rvujc4t.fsf@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Wed, Jan 05, 2022 at 08:00:50PM +0200, Jani Nikula wrote: > On Wed, 05 Jan 2022, Kees Cook wrote: > > The link_status array was not large enough to read the Adjust Request > > Post Cursor2 register, so remove the common helper function to avoid > > an OOB read, found with a -Warray-bounds build: > > > > drivers/gpu/drm/drm_dp_helper.c: In function 'drm_dp_get_adjust_request_post_cursor': > > drivers/gpu/drm/drm_dp_helper.c:59:27: error: array subscript 10 is outside array bounds of 'const u8[6]' {aka 'const unsigned char[6]'} [-Werror=array-bounds] > > 59 | return link_status[r - DP_LANE0_1_STATUS]; > > | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ > > drivers/gpu/drm/drm_dp_helper.c:147:51: note: while referencing 'link_status' > > 147 | u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > > | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > Replace the only user of the helper with an open-coded fetch and decode, > > similar to drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c. > > > > Fixes: 79465e0ffeb9 ("drm/dp: Add helper to get post-cursor adjustments") > > Cc: Maarten Lankhorst > > Cc: Maxime Ripard > > Cc: Thomas Zimmermann > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: dri-devel@lists.freedesktop.org > > Signed-off-by: Kees Cook > > --- > > This is the alternative to: > > https://lore.kernel.org/lkml/20211203084354.3105253-1-keescook@chromium.org/ > > --- > > drivers/gpu/drm/drm_dp_helper.c | 10 ---------- > > drivers/gpu/drm/tegra/dp.c | 11 ++++++++++- > > include/drm/drm_dp_helper.h | 2 -- > > 3 files changed, 10 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > > index 23f9073bc473..c9528aa62c9c 100644 > > --- a/drivers/gpu/drm/drm_dp_helper.c > > +++ b/drivers/gpu/drm/drm_dp_helper.c > > @@ -144,16 +144,6 @@ u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > > } > > EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); > > > > -u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > > - unsigned int lane) > > -{ > > - unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2; > > - u8 value = dp_link_status(link_status, offset); > > - > > - return (value >> (lane << 1)) & 0x3; > > -} > > -EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor); > > - > > static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) > > { > > if (rd_interval > 4) > > diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c > > index 70dfb7d1dec5..f5535eb04c6b 100644 > > --- a/drivers/gpu/drm/tegra/dp.c > > +++ b/drivers/gpu/drm/tegra/dp.c > > @@ -549,6 +549,15 @@ static void drm_dp_link_get_adjustments(struct drm_dp_link *link, > > { > > struct drm_dp_link_train_set *adjust = &link->train.adjust; > > unsigned int i; > > + u8 post_cursor; > > + int err; > > + > > + err = drm_dp_dpcd_read(link->aux, DP_ADJUST_REQUEST_POST_CURSOR2, > > + &post_cursor, sizeof(post_cursor)); > > There's a drm_dp_dpcd_readb() for the common 1-byte reads. Other than > that, > > Reviewed-by: Jani Nikula Thanks! > > Though obviously that's not enough to actually merge to tegra. As in, "a review by Jani isn't sufficient to land via the tegra tree"? What should next steps be? -Kees > > > + if (err < 0) { > > + DRM_ERROR("failed to read post_cursor2: %d\n", err); > > + post_cursor = 0; > > + } > > > > for (i = 0; i < link->lanes; i++) { > > adjust->voltage_swing[i] = > > @@ -560,7 +569,7 @@ static void drm_dp_link_get_adjustments(struct drm_dp_link *link, > > DP_TRAIN_PRE_EMPHASIS_SHIFT; > > > > adjust->post_cursor[i] = > > - drm_dp_get_adjust_request_post_cursor(status, i); > > + (post_cursor >> (i << 1)) & 0x3; > > } > > } > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index 472dac376284..fdf3cf6ccc02 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -1528,8 +1528,6 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI > > int lane); > > u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > > int lane); > > -u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > > - unsigned int lane); > > > > #define DP_BRANCH_OUI_HEADER_SIZE 0xc > > #define DP_RECEIVER_CAP_SIZE 0xf > > -- > Jani Nikula, Intel Open Source Graphics Center -- Kees Cook