From: Prathamesh Shete <pshete@nvidia.com>
To: <linus.walleij@linaro.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <linux-gpio@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <pshete@nvidia.com>, <smangipudi@nvidia.com>, EJ Hsu <ejh@nvidia.com>
Subject: [PATCH] pinctrl: tegra: Set SFIO mode to Mux Register
Date: Fri, 11 Mar 2022 10:00:15 +0530 [thread overview]
Message-ID: <20220311043015.4027-1-pshete@nvidia.com> (raw)
If the device has the 'sfsel' bit field, pin should be
muxed to set to SFIO mode to be used for pinmux operation.
Signed-off-by: EJ Hsu <ejh@nvidia.com>
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
drivers/pinctrl/tegra/pinctrl-tegra.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 50bd26a30ac0..30341c43da59 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -270,6 +270,9 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
val &= ~(0x3 << g->mux_bit);
val |= i << g->mux_bit;
+ /* Set the SFIO/GPIO selection to SFIO when under pinmux control*/
+ if (pmx->soc->sfsel_in_mux)
+ val |= (1 << g->sfsel_bit);
pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
return 0;
--
2.17.1
next reply other threads:[~2022-03-11 4:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 4:30 Prathamesh Shete [this message]
2022-03-23 12:31 ` [PATCH] pinctrl: tegra: Set SFIO mode to Mux Register Thierry Reding
2022-03-28 13:14 ` Linus Walleij
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