From: Ashish Mhetre <amhetre@nvidia.com>
To: <krzysztof.kozlowski@linaro.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <digetx@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<dmitry.osipenko@collabora.com>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <vdumpa@nvidia.com>, <Snikam@nvidia.com>,
Ashish Mhetre <amhetre@nvidia.com>
Subject: [Patch v9 3/4] dt-bindings: memory: tegra: Update validation for reg and reg-names
Date: Tue, 26 Apr 2022 13:08:26 +0530 [thread overview]
Message-ID: <20220426073827.25506-4-amhetre@nvidia.com> (raw)
In-Reply-To: <20220426073827.25506-1-amhetre@nvidia.com>
From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels.
Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers.
So update the reg minItems and maxItems accordingly in tegra186
devicetree documentation. Also update validation for reg-names added for
these corresponding reg items.
ABI change due to new bindings is intended but backward compatibility is
preserved in driver.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
.../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++--
1 file changed, 74 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 13c4c82fd0d3..c7cfa6c2cd81 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,8 +34,12 @@ properties:
- nvidia,tegra234-mc
reg:
- minItems: 1
- maxItems: 3
+ minItems: 6
+ maxItems: 18
+
+ reg-names:
+ minItems: 6
+ maxItems: 18
interrupts:
items:
@@ -142,7 +146,18 @@ allOf:
then:
properties:
reg:
- maxItems: 1
+ maxItems: 6
+ description: 5 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ maxItems: 6
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
- if:
properties:
@@ -151,7 +166,30 @@ allOf:
then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15
- if:
properties:
@@ -160,13 +198,37 @@ allOf:
then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15
additionalProperties: false
required:
- compatible
- reg
+ - reg-names
- interrupts
- "#address-cells"
- "#size-cells"
@@ -182,7 +244,13 @@ examples:
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
- reg = <0x0 0x02c00000 0x0 0xb0000>;
+ reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
+ <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
+ <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
+ <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
+ <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
+ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
--
2.17.1
next prev parent reply other threads:[~2022-04-26 7:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-26 7:38 [Patch v9 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-04-26 7:38 ` [Patch v9 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-04-29 7:11 ` Krzysztof Kozlowski
2022-04-29 8:30 ` Thierry Reding
2022-04-29 8:50 ` Dmitry Osipenko
2022-04-29 10:47 ` Ashish Mhetre
2022-04-26 7:38 ` [Patch v9 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-04-26 7:38 ` Ashish Mhetre [this message]
2022-04-26 7:38 ` [Patch v9 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220426073827.25506-4-amhetre@nvidia.com \
--to=amhetre@nvidia.com \
--cc=Snikam@nvidia.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=dmitry.osipenko@collabora.com \
--cc=jonathanh@nvidia.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=thierry.reding@gmail.com \
--cc=vdumpa@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox